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 Verilog design in Cadence 

Last post Fri, Dec 6 2013 8:52 AM by Sali. 6 replies.
Started by kenambo 29 Oct 2013 12:28 AM. Topic has 6 replies and 3254 views
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  • Tue, Oct 29 2013 12:28 AM

    • kenambo
    • Not Ranked
    • Joined on Thu, Sep 26 2013
    • Tirunelveli, Tamil Nadu
    • Posts 11
    • Points 220
    Verilog design in Cadence Reply

     Hi,

     Is there anyway that i can design a digital circuit in Virtuoso Schematic window...

    And include the *.v file in the schematic capture window..

     

    Thanks...

    Filed under:
    • Post Points: 35
  • Mon, Nov 4 2013 8:00 AM

    Re: Verilog design in Cadence Reply

    Yes. You can create textual Verilog views (File->New->CellView and set the Type to "Verilog" - give the lib/cell/view a name). Then in the resulting editor create the Verilog representation. When you save and exit the editor, it will syntax check the view and then prompt you to create a symbol. You can instantiate this in the schematic.

    Regards,

    Andrew.

     

    • Post Points: 20
  • Thu, Nov 14 2013 4:45 PM

    • Sali
    • Top 500 Contributor
    • Joined on Fri, Nov 1 2013
    • Posts 28
    • Points 365
    Re: Verilog design in Cadence Reply

     Hi all,

    I'm trying to build a voltage controlled curent source,I opened a new file with a verilogAMS text and write the following:

    module VCCS(p,n,pc,nc);
    inout p,n;
    input pc,nc;
    electrical p,n,pc,nc;
    parameter real gain=1;
    branch (p,n) iSrc;
    analog begin
    I(iSrc) <+ gain*V(pc,nc);
    end
    endmodulet pc,nc;

    and I created a symbol for it then I instantiate it on the schematic page but the output is always zero?

    Can any one help me?

    thanks

    • Post Points: 20
  • Sun, Dec 1 2013 11:07 PM

    • kenambo
    • Not Ranked
    • Joined on Thu, Sep 26 2013
    • Tirunelveli, Tamil Nadu
    • Posts 11
    • Points 220
    Re: Verilog design in Cadence Reply

     Thanks.. so i have to write a .v file and create a symbol.. am i right...

    What is the difference between this and the synthesis tool

     

    Thanks,,....

    Filed under: ,
    • Post Points: 20
  • Mon, Dec 2 2013 2:52 AM

    Re: Verilog design in Cadence Reply

    Sali:
    module VCCS(p,n,pc,nc);
    inout p,n;
    electrical p,n,pc,nc;
    parameter real gain=1;
    branch (p,n) iSrc;
    analog begin
    I(iSrc) <+ gain*V(pc,nc);
    end
    endmodulet pc,nc;

    Not sure why you posted this on the end of another thread, but the code you posted has typos in it - it wouldn't even syntax compile. I used a command-line example to try this out (having fixed the typos):

    `include "disciplines.vams"

    module VCCS(p,n,pc,nc);
    inout p,n;
    input pc,nc;
    electrical p,n,pc,nc;
    parameter real gain=1;
    branch (p,n) iSrc;
    analog begin
    I(iSrc) <+gain*V(pc,nc);
    end
    endmodule

    module test;
    electrical gnda;
    ground gnda;

    vsource #(.freq(1M),.ampl(0.5), .type("sine")) V1(n1,gnda);
    resistor #(.r(1k)) R1(op1,gnda);
    VCCS #(.gain(1m)) I1(op1,gnda,n1,gnda);

    endmodule

    And this together with testVCCS.scs :

    tran tran stop=2u

    I then ran "irun -gui testVCCS.scs testVCCS.vams" and I see these results (having problems uploading the picture, so I'll try again in a moment). Looks pretty OK to me.

    Andrew.

     

     


    input pc,nc;
    • Post Points: 5
  • Mon, Dec 2 2013 3:02 AM

    Re: Verilog design in Cadence Reply

    kenambo:

     Thanks.. so i have to write a .v file and create a symbol.. am i right...

    What is the difference between this and the synthesis tool

     

    A synthesis tool takes RTL (Register Transfer Level) code and converts it into a gate level representation. Writing a Verilog text view and simulating that just means that you're simulating what you wrote without it being synthesized. So it's a bit like asking what is the difference between an orange and a car - two completely different things.

    Regards,

    Andrew.

     

    • Post Points: 20
  • Fri, Dec 6 2013 8:52 AM

    • Sali
    • Top 500 Contributor
    • Joined on Fri, Nov 1 2013
    • Posts 28
    • Points 365
    Re: Verilog design in Cadence Reply
    Thank you so much Andrew, and sorry for being late in my reply I had a problem accessing my cadence account ant it solved now. Thank you again, Sali
    • Post Points: 5
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Started by kenambo at 29 Oct 2013 12:28 AM. Topic has 6 replies.