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 interconnect check with PSL  

Last post Wed, Oct 23 2013 7:39 AM by ckomar. 1 replies.
Started by bjerkely 23 Oct 2013 01:04 AM. Topic has 1 replies and 3454 views
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  • Wed, Oct 23 2013 1:04 AM

    • bjerkely
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    interconnect check with PSL Reply

    Hi all,

     I want to check interconnectivity among several IP blocks(in VHDL and Verilog) with PSL vunits. However I have a problem in binding. As I understand, i can bind the vunit to only one entity. But for interconnect check, I need port signals from both entities(IPs) so that I can continiously compare them. I can achieve this with SVA using SystemVerilog interfaces, but in PSL I am stuck.

     Thanks for your help in advance,

     BJ

     

     

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  • Wed, Oct 23 2013 7:39 AM

    • ckomar
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    • Joined on Thu, Jul 17 2008
    • Phoenix, AZ
    • Posts 11
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    Re: interconnect check with PSL Reply

    Hi BJ,

     The problem you face is likely how to specify out-of-module references. This can be done with nc_mirrors. This way you can "bind" to one entity but see any entity/module signal via the mirror call.  That said, I did want to mention that Cadence has a pre-packaged verification app that addresses this problem directly. You can get more info on this verification app in a few ways

    1) contact your local AE

    2) watch a webinar about the solution: https://www.cadence.com/cadence/events/Pages/registration.aspx?eventid=516

    3) review the Rapid Adoption Kit found on http://support.cadence.com.   Under "Resources" you will see "Rapid Adoption Kits". Clicking the "SOC and IP level Functional Verification" link you see a kit for "SoC Connectivity Application

     Thanks,

    Chris 

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Started by bjerkely at 23 Oct 2013 01:04 AM. Topic has 1 replies.