I can't tell whether 10kHz is low enough in frequency from the information you've given. If you want 3000 cycles, you need to go down as low as Fcycle/3000 - so if your clock is above 30MHz, you'll be OK.Originally posted in cdnusers.org by adbeckett
Since the jitter is coming from the noise analysis that is done, there is no need to simulate more cycles in the time domain. A single cycle of the output clock will be enough to capture the non-linearities so that pnoise can include all the noise folding that occurs in the circuit. It can then compute the noise response over frequency, and the k-cycle jitter will be dependent on integrating over that number of cycles (but in the frequency domain). So provided you have simulated the pnoise low enough in frequency to capture the noise at that fraction of your clock frequency, you'll be OK. The integration itself is far from trivial, but the pnoise form takes care of that - you just need to ensure that the frequency range is wide enough, and that it you've asked for the number of cycles you want.
The result should be realistic (in terms of the the random jitter). You won't of course be capturing any deterministic jitter this way.