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 Max Transition Violations in CTS report 

Last post Mon, Nov 18 2013 1:14 PM by Bardia B. 2 replies.
Started by Bardia B 17 Oct 2013 01:41 PM. Topic has 2 replies and 3874 views
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  • Thu, Oct 17 2013 1:41 PM

    • Bardia B
    • Not Ranked
    • Joined on Mon, Jan 3 2011
    • Posts 7
    • Points 95
    Max Transition Violations in CTS report Reply

    Hi,

    I use Automatic gated CTS, and it is recommended by my foundry to set maxsinktran and maxbuftran to 2ns. Also I've found that the required maxtran is 4ns by my library.

     After running CTS, there are some max tran violations in the CTS report for some of my clocks. like below: 

    Max. Rise Sink Tran            : 2335.1(ps)             2000(ps)            

    However I do not see any violations in the postCTS timedesign report.  Is this because this is still below 4ns which is the global target for max tran?

     should I take these max tran violations in the CTS report seriously?

     How can I remove this violations during CTS?

     Also another interesting point is that after running CTS for one of my clocks, I got the following report: 

     ###############################################################

    # Complete Clock Tree Timing Report

    #

    # CLOCK: PCLK

    #

    # Mode: preRoute

    #

    # Delay Corner information

    # Analysis View       : func_max

    # Delay Corner Name   : corner_max

    # RC Corner Name      : ams_rc_corner_wc

    # Analysis View       : func_min

    # Delay Corner Name   : corner_min

    # RC Corner Name      : ams_rc_corner_bc

    ###############################################################

     

     

    Nr. of Subtrees                : 5

    Nr. of Sinks                   : 672

    Nr. of Buffer                  : 32

    Nr. of Level (including gates) : 8

    Root Rise Input Tran           : 0.1(ps)

    Root Fall Input Tran           : 0.1(ps)

    Max trig. edge delay at sink(R): CoeffMEM/Reg_in_reg[9]/CP 5064.6(ps)

    Min trig. edge delay at sink(R): CoeffMEM/C2_mem_reg[17][6]/CP 4775.7(ps)

     

                                     (Actual)               (Required)          

    Rise Phase Delay               : 4775.7~5064.6(ps)      1000~10000(ps)      

    Fall Phase Delay               : 4329.3~4991.3(ps)      1000~10000(ps)      

    Trig. Edge Skew                : 288.9(ps)              200(ps)             

    Rise Skew                      : 288.9(ps)              

    Fall Skew                      : 662(ps)                

    Max. Rise Buffer Tran          : 1223.2(ps)             2000(ps)            

    Max. Fall Buffer Tran          : 834.3(ps)              2000(ps)            

    Max. Rise Sink Tran            : 1094.5(ps)             2000(ps)            

    Max. Fall Sink Tran            : 776.9(ps)              2000(ps)            

    Min. Rise Buffer Tran          : 113(ps)                0(ps)               

    Min. Fall Buffer Tran          : 105.1(ps)              0(ps)               

    Min. Rise Sink Tran            : 601.4(ps)              0(ps)               

    Min. Fall Sink Tran            : 477.9(ps)              0(ps)               

     

    view func_max : skew = 288.9ps (required = 200ps)

    view func_min : skew = 197.9ps (required = 200ps)

     

     

     

     

    ***** Max Transition Time Violation *****

     

    Pin Name                         (Actual)               (Required)          

    -------------------------------------------------------------------

    PCLK__L1_I0/A                    [4008 2176.2](ps)      2000(ps)            

    PCLK__L1_I1/A                    [4008 2176.2](ps)      2000(ps)            

     

     

     

    ***** NO Min Transition Time Violation *****

     

    ***** NO Max Capacitance Violation *****

     

    ***** NO Max_Fanout Violation *****

     

    ***** NO AC Irms Limit Violation *****

     

    as you see above, in the Max Rise/Fall Buffer Tran the maximum transition is met, but at the end it reports two pin names which violate the transition time. I don't how this makes sense! 

     So again here this violation does not exist in the timedesign report of postCTS even though it is larger than 4ns!!!

    So can you help me with these issues?

     Thank you so much in advance,

    Bardia 

    • Post Points: 20
  • Mon, Nov 18 2013 12:29 PM

    • fitz
    • Top 150 Contributor
    • Joined on Wed, Aug 4 2010
    • Kanata, Ontario
    • Posts 56
    • Points 745
    Re: Max Transition Violations in CTS report Reply

     Bardia:

     PCLK__L1 is the first level of your clock tree, what is driving this initial 4000ps rising edge? Is it an actual cell or a boundary constraint?

    If it is a boundary constraint,  correct the constraint ie, less than your 2000ps target.

    If it is an actual driver cell you probably need to add an additional "L0" clock buffer level . I found that a "AddDriverCell < CLK_BUF_TYPE>"  entry in the .ctstch control file helps this situation a lot.

     Shawn

     

    • Post Points: 20
  • Mon, Nov 18 2013 1:14 PM

    • Bardia B
    • Not Ranked
    • Joined on Mon, Jan 3 2011
    • Posts 7
    • Points 95
    Re: Max Transition Violations in CTS report Reply
    Thanks Shawn for your help!
    • Post Points: 5
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Started by Bardia B at 17 Oct 2013 01:41 PM. Topic has 2 replies.