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 DDR2 and DDR3 connections 

Last post Mon, Oct 7 2013 12:24 AM by akael. 2 replies.
Started by akael 06 Oct 2013 01:50 AM. Topic has 2 replies and 430 views
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  • Sun, Oct 6 2013 1:50 AM

    • akael
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    • Joined on Sun, Aug 4 2013
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    • Points 25
    DDR2 and DDR3 connections Reply

     Hi, I'm quite confused about´╗┐ schematic with DDR2 or DDR3 memory, I've checked several design, and some design have the pin D0 of the chip memory connected to net MDQ0,D1 connected to MDQ1 ( the other pins have the same logic, with the respective number bit) , so i can understand it , BUT OTHER DESIGN ARE VERY DIFFERENT , just for example the pin D0 of the chip memory is connected to MDQ5, D1 connected to MDQ7 ..., it's another technique, there is logic for this? pls i hope someone can help me.

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    • Post Points: 20
  • Sun, Oct 6 2013 6:09 AM

    • tltoth
    • Top 50 Contributor
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    • Miskolc, Hungary
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    Re: DDR2 and DDR3 connections Reply

     Data lines within the same byte-lane can be swapped to ease the routing

    • Post Points: 20
  • Mon, Oct 7 2013 12:24 AM

    • akael
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    • Joined on Sun, Aug 4 2013
    • Posts 2
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    Re: DDR2 and DDR3 connections Reply

     Thanks for your answerd , i think i couldn't find a information because of I didn't use the keyword " byte-lane can be swapped", now i found it.

    • Post Points: 5
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Started by akael at 06 Oct 2013 01:50 AM. Topic has 2 replies.