We are using AMS Designer for high level verification on a chip with many analog blocks as well as two digital voltage domains.
We are invoking AMS Designer from ADE.
Now, when applying a digital (VerilogD) clock, we do see ripple on the analog power supply even thou we do not have any impedance on the power supply.(In reality we may have some impedance on the power supply but not in our simpler verilog-ams models.)
It seems like the modules(?) automatically inserted by the connect library cannot tell signal sources from power supply sources. (How could it? We have not told the netlister which is which.) Can we force this by any action?
It seems like a waste of CPU time to calculate the ripple when it should not be there.
/CGOriginally posted in cdnusers.org by cgthisell