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 Layout pin problem: net name distributes via transistor 

Last post Fri, Sep 20 2013 2:38 PM by jeffreyprin. 0 replies.
Started by jeffreyprin 20 Sep 2013 02:38 PM. Topic has 0 replies and 352 views
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  • Fri, Sep 20 2013 2:38 PM

    Layout pin problem: net name distributes via transistor Reply

    Hi,

    I am facing a problem in the layout. I designed a DRC free inverter using the gpdk90nm package from pdk.cadence. 

    The final step of placing pins in the circuit invokes net connection errors. When the Out pin of the inverter is placed on the layout, the metal of vdd (not yet assigned) and gnd (not yet assigned) also gets the net name "Out". Even the active layer and all contacts get the Out net name. After placing the vdd! and gnd! pins on their metal, there is an error that the nets do not match (because the net has Out net name).

     Why is the Out net distributed via the thansistor (eg from drain to source).

     

    If for example a third nmos transistor is drawn next to the inverter (see figure below). before connecting the ground wire, all the layers of that transistor have no net name. When connecting the metal 1 form gnd! to one of the transistor contacts, the other contact also get gnd! net name what should not be. (you can see that the net is distributed to the other contact by the green lines). the active layer than also gets the gnd! net name...

     

    I am using ic6.14 running on CentOS 64bit.

     

    Thanks in advance

     

    Jeffrey

     

     

    example

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Started by jeffreyprin at 20 Sep 2013 02:38 PM. Topic has 0 replies.