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 Instantiating VHDL with record port in SystemVerilog testbench 

Last post Thu, Sep 19 2013 4:01 PM by xoroc. 0 replies.
Started by xoroc 19 Sep 2013 04:01 PM. Topic has 0 replies and 8006 views
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  • Thu, Sep 19 2013 4:01 PM

    • xoroc
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    • Joined on Wed, Sep 18 2013
    • Posts 1
    • Points 5
    Instantiating VHDL with record port in SystemVerilog testbench Reply

    The VHDL code I am verifying has some of the ports defined in a VHDL record.

    How do I reference these signals in a SystemVerilog testbench?

    • Post Points: 5
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Started by xoroc at 19 Sep 2013 04:01 PM. Topic has 0 replies.