The important thing is not about how to use #data[i].
It's how transfer a integer i from the top file in verilog to the inner module writen by VHDL.
As the code shows bellow:
At test bench top file which was written in verilog:
for (i=0, i < 4096, i=i+1) begin
The array mem_int is beneth vhdl designed module, so my question is how can I transfer
the integer i to VHDL designed module mem_int?