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 ploting/saving Verilog-A variables with AMS simulator using Ultrasim Solver 

Last post Mon, Sep 16 2013 11:18 PM by aarthymani. 0 replies.
Started by aarthymani 16 Sep 2013 11:18 PM. Topic has 0 replies and 4810 views
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  • Mon, Sep 16 2013 11:18 PM

    • aarthymani
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    • Joined on Wed, Nov 16 2011
    • Singapore, 00-SG
    • Posts 8
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    ploting/saving Verilog-A variables with AMS simulator using Ultrasim Solver Reply

    Hi,

    I am trying to save the verilog-A variables in using AMS with Ultrasim solver, as the saveahdlvars doesn't work, I used .probe statement as per this http://www.cadence.com/Community/forums/p/14932/26102.aspx discussion. But the suggestions works well when the simulator is pure ultrasim. When I change to AMS with Ultrasim, the .probe statement doesn't seams to work.

    I used, simulator lang = spice lookup=spectre 

              .probe tran all(I0.I2.I*.I*.I2)

    I included the file containing the above using setup --> simulation files --> include files option in ADE. But when I create the netlist, the file is not at all available in the netlist. 

     What is the mistake here? Someone help!! 

     

     

     

    Regards, Aarthy
    • Post Points: 5
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Started by aarthymani at 16 Sep 2013 11:18 PM. Topic has 0 replies.