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 ISFET layout design 

Last post Tue, Sep 17 2013 6:18 AM by Quek. 1 replies.
Started by ronaldomponte 16 Sep 2013 05:56 PM. Topic has 1 replies and 246 views
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  • Mon, Sep 16 2013 5:56 PM

    • ronaldomponte
    • Not Ranked
    • Joined on Mon, Mar 11 2013
    • Florianopolis, 00-BR
    • Posts 8
    • Points 130
    ISFET layout design Reply

    Hello,

    Is it possible to design an ISFET sensor thru Cadence Design Enviroment tools? 

    If it is possible, I guess it may be necessary to breach some design rules, isn't it?

    Could anyone guide me thru this specific design? How can I breach the design rules? Is it possible to coat different materials (e.g. Si3N4) over the gate insulator? How about the layout?

    Thank you very much.

    Best regards.  

    • Post Points: 20
  • Tue, Sep 17 2013 6:18 AM

    • Quek
    • Top 10 Contributor
    • Joined on Wed, Oct 14 2009
    • Singapore, 00-SG
    • Posts 1,060
    • Points 16,110
    Re: ISFET layout design Reply

    Hi Ronald

    Yes, it is possible to design an ISFET sensor using Virtuoso platform. I googled for "ISFET spectre simulation" and found quite a number of research papers written using Virtuoso. E.g.

    CMOS readout circuitry for ISFET microsystems

    I think you should contact a suitable foundry and get a process design kit (PDK). The kit should contain the information which you need.

    Best regards
    Quek

    • Post Points: 5
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Started by ronaldomponte at 16 Sep 2013 05:56 PM. Topic has 1 replies.