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 What does Constant hierarchical Pin(s) means in RTL compiler? 

Last post Wed, Sep 11 2013 10:48 AM by bmiller. 1 replies.
Started by Bardia B 09 Sep 2013 11:47 AM. Topic has 1 replies and 8008 views
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  • Mon, Sep 9 2013 11:47 AM

    • Bardia B
    • Not Ranked
    • Joined on Mon, Jan 3 2011
    • Posts 7
    • Points 95
    What does Constant hierarchical Pin(s) means in RTL compiler? Reply
    Hi everybody,

    When I check the design in RTL compiler 10.1 after synthesis, I get the following summary for my design.

    I know that Assigns are not good and should be removed before importing the design in SoC encounter and I know how to do it.

    But my question is about the Constant hierarchical Pin(s). I don't know what those mean and if they are important? Should they also be removed before place and route? And how?


    Name Total 
    -------------------------------------------
    Unresolved References 0 
    Empty Modules 0 
    Unloaded Port(s) 0 
    Unloaded Sequential Pin(s) 0 
    Assigns 83 
    Undriven Port(s) 0 
    Undriven Leaf Pin(s) 0 
    Undriven hierarchical pin(s) 0 
    Multidriven Port(s) 0 
    Multidriven Leaf Pin(s) 0 
    Multidriven hierarchical Pin(s) 0 
    Multidriven unloaded net(s) 0 
    Constant Port(s) 0 
    Constant Leaf Pin(s) 3 
    Constant hierarchical Pin(s) 297 
    Preserved leaf instance(s) 0 
    Preserved hierarchical instance(s) 0 
    Libcells with no LEF cell 0 
    Physical (LEF) cells with no libcell 27
     
    Thanks in advance for your help.
     Bardia 
    • Post Points: 20
  • Wed, Sep 11 2013 10:48 AM

    • bmiller
    • Top 200 Contributor
    • Joined on Tue, Oct 14 2008
    • Ottawa, Ontario
    • Posts 42
    • Points 570
    Re: What does Constant hierarchical Pin(s) means in RTL compiler? Reply

     Constant hierarchical pins are generally not a problem, but they are still worth investigating.  When RC propagates constants across hierarchical boundaries, it will tie the pin to 1'b0.  The other side of that hierarchical pin will have nothing attached to it.  It effectively becomes an unused hierarchical pin, but RC, by default, will tie it off so it is not undriven.

     What you need to do, to further investigate, is run "check_design -constant" and look at any constant hierarchical pins have a fanout greater than 0.  A fanout of 0 means that it is an unused hier pin, which is not an issue.  For example:

     

    design 'dtmf_chip' has the following constant input hierarchical pin(s)
    /designs/dtmf_chip/instances_hier/JTAG_MODULE/pins_in/JTAG_SE      (fanout : 5)
    /designs/dtmf_chip/instances_hier/JTAG_MODULE/pins_in/JTAG_TEST_ENABLE      (fanout : 4)
    /designs/dtmf_chip/instances_hier/JTAG_MODULE/pins_in/JTAG_IOTEST      (fanout : 1)
    /designs/dtmf_chip/instances_hier/JTAG_MODULE/pins_in/JTAG_TEST_CLOCK      (fanout : 1)
    /designs/dtmf_chip/instances_hier/JTAG_MODULE/pins_in/JTAG_INSTR_CAPTURE_2      (fanout : 1)
    /designs/dtmf_chip/instances_hier/JTAG_MODULE/pins_in/JTAG_POR      (fanout : 1)
    /designs/dtmf_chip/instances_hier/DTMF_INST3/pins_in/tdsp_pso      (fanout : 0)
    /designs/dtmf_chip/instances_hier/DTMF_INST3/pins_in/int      (fanout : 0)
    /designs/dtmf_chip/instances_hier/DTMF_INST2/pins_in/tdsp_pso      (fanout : 0)
    /designs/dtmf_chip/instances_hier/DTMF_INST2/pins_in/int      (fanout : 0)
    /designs/dtmf_chip/instances_hier/DTMF_INST1/pins_in/tdsp_pso      (fanout : 0)

     

    In this case, some of the JTAG_MODULE pins are tied off, which I expect, and all the rest of a fanout of 0.  No problems here.

     

    • Post Points: 5
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Started by Bardia B at 09 Sep 2013 11:47 AM. Topic has 1 replies.