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 Error in Simulating Verilog XL+Analog in spectreVerilog 

Last post Wed, Sep 4 2013 1:54 PM by Andrew Beckett. 2 replies.
Started by ksnf3000 04 Sep 2013 09:53 AM. Topic has 2 replies and 320 views
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  • Wed, Sep 4 2013 9:53 AM

    • ksnf3000
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    • Joined on Tue, Oct 30 2012
    • Posts 13
    • Points 200
    Error in Simulating Verilog XL+Analog in spectreVerilog Reply

    Hello All,

    I am trying to do a simulation of a circuit which involves analog circuits,veriloga model and a verilog model. However, I am stuck with the following 2 (please see the attachment).

    FYI the simulator I am using is spectreVerilog

    I keep getting this error. Please let me know any way to solve this. 

    Thanks,

    Kashif

     


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    • Post Points: 5
  • Wed, Sep 4 2013 9:55 AM

    • ksnf3000
    • Not Ranked
    • Joined on Tue, Oct 30 2012
    • Posts 13
    • Points 200
    Error in Simulating Verilog XL+Analog in spectreVerilog Reply

    Hello All,

    I am trying to do a simulation of a circuit which involves analog circuits,veriloga model and a verilog model. However, I am stuck with the following 2 (please see the attachment).

    FYI the simulator I am using is spectreVerilog

    I keep getting this error. Please let me know any way to solve this. 

    Thanks,

    Kashif
    Filed under:
    • Post Points: 20
  • Wed, Sep 4 2013 1:54 PM

    Re: Error in Simulating Verilog XL+Analog in spectreVerilog Reply

    Kashif

    First of all, the forum guidelines at http://www.cadence.com/community/forums/T/19839.aspx and in each forum tell you not to post to multiple forums. So I have merged them together. 

    What views do you have of each of the cells? Were there any messages during netlisting? Have you checked the partitioning?

     Regards,

    Andrew 

    • Post Points: 5
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Started by ksnf3000 at 04 Sep 2013 09:53 AM. Topic has 2 replies.