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 Error in verilogA 

Last post Tue, Sep 3 2013 9:40 PM by sreeni. 4 replies.
Started by sreeni 03 Sep 2013 08:58 AM. Topic has 4 replies and 253 views
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  • Tue, Sep 3 2013 8:58 AM

    • sreeni
    • Not Ranked
    • Joined on Wed, May 15 2013
    • Posts 6
    • Points 90
    Error in verilogA Reply

    Hi to all

    Am designing one model in verilog-A. 

    In that i have defined one function (Charge_low) and while using it in the main design it showing some error.

    Am not able to understand the error.

     hsp-vacomp: Error: syntax error

     hsp-vacomp:     ['SBCNTFET.va',399]

     hsp-vacomp:     Qs_low1 = Charge_low(  2.32  ,H1,b1_1,b0_1)-Charge_low(`alpha_1,L1,b1_1,b0_1);
     hsp-vacomp:                                                         ^

     Error was showing @ the "," after H1.

    All variables in the function are declared as real and defined.

    Please let me know what may be the error.

     

    Thanks

    SRINI

     

    • Post Points: 20
  • Tue, Sep 3 2013 9:04 AM

    Re: Error in verilogA Reply

    Two problems:

    1. The error is coming from the HSPICE veriloga compiler. Given that HSPICE is a Synopsys product, asking about it on a Cadence forum is probably not the best place to ask. We can try, but you're likely to get more accurate answers on a Synopsys forum
    2. You didn't show the code - it's impossible to debug from just a single line...

    Regards,

    Andrew.

    • Post Points: 20
  • Tue, Sep 3 2013 9:17 AM

    • sreeni
    • Not Ranked
    • Joined on Wed, May 15 2013
    • Posts 6
    • Points 90
    Re: Error in verilogA Reply

     Hi Andrew,

    I got habituated to post in cadence forum.

    My code is of some 600 lines i can't post it.

    Am adding few more lines of that function declaration and where am getting error.

     

    analog function real eeta;
            input x,y;
            real x,y;
            begin
                eeta  = hspsqrt(x*y*y+y);
            end
        endfunction 

        /*************************************************************************/
       
       
        analog function charge_low;
        input x,y,b1,bo;
        real x,y,b1,bo;
          begin
             charge_low = eeta(x,y)*((b1*(y-(1/2*x)))+(2*b0))+((b1)/(4*hsppow(x,1.5)))* hspln(((0.5+(x*y))/(hspsqrt(x)))+(eeta(x,y)));
           end
        endfunction

     I posted 'eeta' function also, as a refence.

     And here is those lines where it showing error.

     

    Qs_low1 = Charge_low(`alpha_1,H1,b1_1,b0_1)-Charge_low(`alpha_1,L1,b1_1,b0_1);

    Please clarify this.

     Thanks

    SRINI

     

    • Post Points: 20
  • Tue, Sep 3 2013 9:57 AM

    Re: Error in verilogA Reply

    Srini,

    Again, you didn't really give enough to be sure, but I corrected two mistakes in what you sent me:

    1. The function charge_low had an input called "bo" but in the expression, it's called "b0".
    2. The function is defined as "charge_low" but called as "Charge_low". Verilog-A is case sensitive.

    I then assembled a simple example module using both these, with some definitions for `alpha_1 and the other arguments:

     `include "disciplines.vams"

    module forum (x);
    input x;
    electrical x;

    analog function real hspsqrt;
      input a;
      real a;
      hspsqrt=sqrt(a);
    endfunction

    analog function real hsppow;
      input a,b;
      real a,b;
      hsppow=pow(a,b);
    endfunction

    analog function real hspln;
      input a;
      real a;
      hspln=ln(a);
    endfunction

    analog function real eeta;
            input x,y;
            real x,y;
            begin
                eeta  = hspsqrt(x*y*y+y);
            end
        endfunction

    analog function charge_low;
    //input x,y,b1,bo;
    //real x,y,b1,bo;
    input x,y,b1,b0;
    real x,y,b1,b0;
      begin
         charge_low = eeta(x,y)*((b1*(y-(1/2*x)))+(2*b0))+((b1)/(4*hsppow(x,1.5)))* hspln(((0.5+(x*y))/(hspsqrt(x)))+(eeta(x,y)));
       end
    endfunction

    `define alpha_1 2.32


    real H1,b1_1,b0_1,L1,Qs_low1;

    analog begin
        @(initial_step) begin
            H1=1.0;
            b1_1=1.0;
            b0_1=1.0;
            L1=1.0;
            //Qs_low1 = Charge_low(`alpha_1,H1,b1_1,b0_1)-Charge_low(`alpha_1,L1,b1_1,b0_1);
            Qs_low1 = charge_low(`alpha_1,H1,b1_1,b0_1)-charge_low(`alpha_1,L1,b1_1,b0_1);
        end

        V(x) <+ 1.0;
    end

    endmodule

    With spectre, I created this netlist:

    //

    thing (n1) forum
    r1 (n1 0) resistor r=1k

    ahdl_include "forum.va"

    dc dc

    And spectre was quite happy when I ran this. So you need to take this up with Synopsys - assuming that you've corrected the typos I mentioned earlier and that doesn't fix it. Note I had to define all those hspsqrt, hspln, hsppow functions because they don't exist in the standard language. So probably Synopsys customer support is your best bet.

    Kind Regards,

    Andrew.

    • Post Points: 20
  • Tue, Sep 3 2013 9:40 PM

    • sreeni
    • Not Ranked
    • Joined on Wed, May 15 2013
    • Posts 6
    • Points 90
    Re: Error in verilogA Reply

     Hi Andrew,

    What ever you mentioned 1 and 2 were the errors. And now its bug free.

    Thank you so much

     When it showing error in one line i was thinking of same line not the actual function.

    Once again thanks 

     Regards

    SRINI

    • Post Points: 5
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Started by sreeni at 03 Sep 2013 08:58 AM. Topic has 4 replies.