Again, you didn't really give enough to be sure, but I corrected two mistakes in what you sent me:
- The function charge_low had an input called "bo" but in the expression, it's called "b0".
- The function is defined as "charge_low" but called as "Charge_low". Verilog-A is case sensitive.
I then assembled a simple example module using both these, with some definitions for `alpha_1 and the other arguments:
module forum (x);
analog function real hspsqrt;
analog function real hsppow;
analog function real hspln;
analog function real eeta;
eeta = hspsqrt(x*y*y+y);
analog function charge_low;
charge_low = eeta(x,y)*((b1*(y-(1/2*x)))+(2*b0))+((b1)/(4*hsppow(x,1.5)))* hspln(((0.5+(x*y))/(hspsqrt(x)))+(eeta(x,y)));
`define alpha_1 2.32
//Qs_low1 = Charge_low(`alpha_1,H1,b1_1,b0_1)-Charge_low(`alpha_1,L1,b1_1,b0_1);
Qs_low1 = charge_low(`alpha_1,H1,b1_1,b0_1)-charge_low(`alpha_1,L1,b1_1,b0_1);
V(x) <+ 1.0;
With spectre, I created this netlist:
thing (n1) forum
r1 (n1 0) resistor r=1k
And spectre was quite happy when I ran this. So you need to take this up with Synopsys - assuming that you've corrected the typos I mentioned earlier and that doesn't fix it. Note I had to define all those hspsqrt, hspln, hsppow functions because they don't exist in the standard language. So probably Synopsys customer support is your best bet.