Srini,
Again, you didn't really give enough to be sure, but I corrected two mistakes in what you sent me:
- The function charge_low had an input called "bo" but in the expression, it's called "b0".
- The function is defined as "charge_low" but called as "Charge_low". Verilog-A is case sensitive.
I then assembled a simple example module using both these, with some definitions for `alpha_1 and the other arguments:
`include "disciplines.vams"
module forum (x);
input x;
electrical x;
analog function real hspsqrt;
input a;
real a;
hspsqrt=sqrt(a);
endfunction
analog function real hsppow;
input a,b;
real a,b;
hsppow=pow(a,b);
endfunction
analog function real hspln;
input a;
real a;
hspln=ln(a);
endfunction
analog function real eeta;
input x,y;
real x,y;
begin
eeta = hspsqrt(x*y*y+y);
end
endfunction
analog function charge_low;
//input x,y,b1,bo;
//real x,y,b1,bo;
input x,y,b1,b0;
real x,y,b1,b0;
begin
charge_low = eeta(x,y)*((b1*(y-(1/2*x)))+(2*b0))+((b1)/(4*hsppow(x,1.5)))* hspln(((0.5+(x*y))/(hspsqrt(x)))+(eeta(x,y)));
end
endfunction
`define alpha_1 2.32
real H1,b1_1,b0_1,L1,Qs_low1;
analog begin
@(initial_step) begin
H1=1.0;
b1_1=1.0;
b0_1=1.0;
L1=1.0;
//Qs_low1 = Charge_low(`alpha_1,H1,b1_1,b0_1)-Charge_low(`alpha_1,L1,b1_1,b0_1);
Qs_low1 = charge_low(`alpha_1,H1,b1_1,b0_1)-charge_low(`alpha_1,L1,b1_1,b0_1);
end
V(x) <+ 1.0;
end
endmodule
With spectre, I created this netlist:
//
thing (n1) forum
r1 (n1 0) resistor r=1k
ahdl_include "forum.va"
dc dc
And spectre was quite happy when I ran this. So you need to take this up with Synopsys - assuming that you've corrected the typos I mentioned earlier and that doesn't fix it. Note I had to define all those hspsqrt, hspln, hsppow functions because they don't exist in the standard language. So probably Synopsys customer support is your best bet.
Kind Regards,
Andrew.