I have already followed successfully some manual which basically talks about how to import the Verilog design which references the standard cell primitives contained in the LEF file. So I import the LEF file, and the .v file, and get the whole thing placed and routed. But that manual is about some generic NCSU-type format.
I now want to try similar thing, but specific to my design kit. The design kit is just a PDK from IBM for 7rf process.
I opened the LEF file provided by the kit, and noticed that there are no standard cell primitives description, as it was a case with LEF file from NCSU with which manual I followed was provided. All I find in the Design Kit's LEF file is description of some rules and layers.
So I assume that there has to be a way of entering the standard cell primitives in that LEF file?
If yes, then what is the smart and proper way of doing it?
Design kit also provides HDL files for the timing/behavior description of each standard cell as well as one big GDS file.
What would be the typical flow to make it all functional? in other words, to somehow let the encounter know about my standard cell files? (again because Design Kit's LEF file has only layer/rule iniformation)