What is the best way to convert the result of saveNetlist -phys to CDL?
Because the way I did it:
1) Import physical verilog to CIW as schematics
2) There from schematics create CDL netlist, then CDL netlist for LVS using preprocessor supplied by kit (the way I always produce netlist for LVS on all my hand made analog circuits, and that way works of course)
But there is a problem, first of all, even though schematics is created and looks big and have all those standard cells, when I tried to look inside those standard cells out of which my big schematics imported from physical Verilog composed I noticed there are NO TRANSISTORS, just ports... is this normal? This looks suspicious to me.
Anyway, I still tried from now on to do the LVS as I always do on all my cusotm circuits, but the LVS spits out errors something like: nfet(MOS) on Layout is unbound to any Schematic device..
So, the bottom line is, after Encounter import, the layout was corrected for residual DRC errors and was looking sexy, the physical Verilog produced by Encounter was imported, schematics of my big digital unit created on a gate level, but each gate had empty schematic inside, and LVS gave that error above.
Why would that happen? And the big question is, how do I import the physical verilog so that the CDL schematics with transistors is created, so that I can do the LVS, because the layout from transistors of course requires schematics with transistors at the bottom level for successfull LVS.