Presently, I am trying to design a Charge Pump Circuit for use in PLL.
I encountered some challenges where regardless of the UP or Down pulse width variations, my Vout will always be increase and stable at 1.1V.
My understanding was that the Vout will increase when UP pulse is wider than Down pulse, while Vout decrease while Down pulse is wider than Up pulse. Vout will be stable when UP and Down pulse is equal.
Would appreciate your advice and recommendations. Thanks.