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 Does clock power included in Power Report ? 

Last post Mon, Jul 29 2013 10:02 AM by dkhan. 2 replies.
Started by dkhan 27 Jul 2013 02:23 PM. Topic has 2 replies and 4016 views
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  • Sat, Jul 27 2013 2:23 PM

    • dkhan
    • Not Ranked
    • Joined on Thu, Jun 13 2013
    • Posts 10
    • Points 140
    Does clock power included in Power Report ? Reply

    Hi All,

    I am conserned whether my power reports include clock power or I have to calculate it separately. Currently I am defining clock period using "define_clock" command before loading my Netlist and then using "report power" command, however when RC loads the VCD file it shows 0.0% activity for clock while asserted signals are at 100%.   

    • Post Points: 20
  • Mon, Jul 29 2013 6:53 AM

    • grasshopper
    • Top 25 Contributor
    • Joined on Fri, Jul 18 2008
    • Chelmsford, MA
    • Posts 241
    • Points 3,200
    Re: Does clock power included in Power Report ? Reply

     Hi dkhan,

    unfortunately the answer is "It depends" If you are using a netlist and also annotating all parasitics, you will effectively have the clock tree accounted for but if you do not annotate parasitics or working at RTL level, the answer is mostly not. The reason I say mostly is that the CGICs are still traced downstream and on the enable side hence it is hard to really say that there is none of the clock tree accounted for but the key parts or at least some significant parts are not. RC provides the option '-clock_tree' to the command 'report power' for the purpose of estimating a clock tree that has not been inserted yet. It will look something like this

     

    rc:/> set_attr lp_clock_tree_buffers CLKINVX8 /designs/* 
      Setting attribute of design 'emac_plus': 'lp_clock_tree_buffers' = /libraries/slow/libcells/CLKINVX8
    rc:/> set_attr lp_clock_tree_leaf_max_fanout 10 /designs/*
      Setting attribute of design 'emac_plus': 'lp_clock_tree_leaf_max_fanout' = 10
    rc:/> report power -clock_tree -width 200 -heigh 300     
    . . .
    Clock Power Estimation Summary for clock 'clk'
    ==============================================

    ------------------------------------------------------
    Estimate   Leakage (nW)   Dynamic (nW)   Total (nW)  
    ------------------------------------------------------
    Max              13.428    9299298.048    9299311.476

    Leaf Clock Buffers                    70
    Total Clock Buffers                   92

    Estimation Parameters
    =====================

    Clock Buffers Used: CLKINVX8

    Max flops driven by one leaf buffer: 10
    Die width: 200.0 um
    Die height: 300.0 um
    Clock Power Estimation Summary for clock 'rx_clk'
    =================================================

    ------------------------------------------------------
    Estimate   Leakage (nW)   Dynamic (nW)   Total (nW)  
    ------------------------------------------------------
    Max              13.516    3666707.676    3666721.192

    Leaf Clock Buffers                    64
    Total Clock Buffers                   92

    Estimation Parameters
    =====================

    Clock Buffers Used: CLKINVX8

    Max flops driven by one leaf buffer: 10
    Die width: 200.0 um
    Die height: 300.0 um

    Clock Power Estimation Summary for clock 'tx_clk'
    =================================================

    ------------------------------------------------------
    Estimate   Leakage (nW)   Dynamic (nW)   Total (nW)  
    ------------------------------------------------------
    Max               7.946    2882486.746    2882494.692

    Leaf Clock Buffers                    32
    Total Clock Buffers                   54

    Estimation Parameters
    =====================

    Clock Buffers Used: CLKINVX8

    Max flops driven by one leaf buffer: 10
    Die width: 200.0 um
    Die height: 300.0 um

    Info    : Time taken to report power. [RPT-7]
            : 5.00 cpu seconds
     

     hope this helps,

    gh-

    • Post Points: 20
  • Mon, Jul 29 2013 10:02 AM

    • dkhan
    • Not Ranked
    • Joined on Thu, Jun 13 2013
    • Posts 10
    • Points 140
    Re: Does clock power included in Power Report ? Reply

     

    grasshopper:

     Hi dkhan,

    unfortunately the answer is "It depends" If you are using a netlist and also annotating all parasitics, you will effectively have the clock tree accounted for but if you do not annotate parasitics or working at RTL level, the answer is mostly not. The reason I say mostly is that the CGICs are still traced downstream and on the enable side hence it is hard to really say that there is none of the clock tree accounted for but the key parts or at least some significant parts are not. RC provides the option '-clock_tree' to the command 'report power' for the purpose of estimating a clock tree that has not been inserted yet. It will look something like this

     

    rc:/> set_attr lp_clock_tree_buffers CLKINVX8 /designs/* 
      Setting attribute of design 'emac_plus': 'lp_clock_tree_buffers' = /libraries/slow/libcells/CLKINVX8
    rc:/> set_attr lp_clock_tree_leaf_max_fanout 10 /designs/*
      Setting attribute of design 'emac_plus': 'lp_clock_tree_leaf_max_fanout' = 10
    rc:/> report power -clock_tree -width 200 -heigh 300     
    . . .
    Clock Power Estimation Summary for clock 'clk'
    ==============================================

    ------------------------------------------------------
    Estimate   Leakage (nW)   Dynamic (nW)   Total (nW)  
    ------------------------------------------------------
    Max              13.428    9299298.048    9299311.476

    Leaf Clock Buffers                    70
    Total Clock Buffers                   92

    Estimation Parameters
    =====================

    Clock Buffers Used: CLKINVX8

    Max flops driven by one leaf buffer: 10
    Die width: 200.0 um
    Die height: 300.0 um
    Clock Power Estimation Summary for clock 'rx_clk'
    =================================================

    ------------------------------------------------------
    Estimate   Leakage (nW)   Dynamic (nW)   Total (nW)  
    ------------------------------------------------------
    Max              13.516    3666707.676    3666721.192

    Leaf Clock Buffers                    64
    Total Clock Buffers                   92

    Estimation Parameters
    =====================

    Clock Buffers Used: CLKINVX8

    Max flops driven by one leaf buffer: 10
    Die width: 200.0 um
    Die height: 300.0 um

    Clock Power Estimation Summary for clock 'tx_clk'
    =================================================

    ------------------------------------------------------
    Estimate   Leakage (nW)   Dynamic (nW)   Total (nW)  
    ------------------------------------------------------
    Max               7.946    2882486.746    2882494.692

    Leaf Clock Buffers                    32
    Total Clock Buffers                   54

    Estimation Parameters
    =====================

    Clock Buffers Used: CLKINVX8

    Max flops driven by one leaf buffer: 10
    Die width: 200.0 um
    Die height: 300.0 um

    Info    : Time taken to report power. [RPT-7]
            : 5.00 cpu seconds
     

     hope this helps,

    gh-

     


    Thanks gh,

    I am using Netlist and define_clock command, when I run "report power", rc shows following info which says there is no activity in clock nets eventhough the simulation runs fine and I have included all nets when generation VCD/SAIF files in Modelsim.  You said clock_tree command is used to estimate clock nets that are not inserted yet, so are they not included in synthesized netlist? What do you mean by parasitics?, other constraints besides clock period?

     

    Nets/ports asserted in SAIF file : 2881
    Total Nets/ports in SAIF file    : 163806
    -------------------------------------------------------
    Asserted Primary inputs in design              : 1930 (100.00%)
    Total connected primary inputs in design       : 1930 (100.00%)
    -------------------------------------------------------
    Asserted sequential outputs                    : 0 (0.00%)
    Total connected sequential outputs             : 5000 (100.00%)
    -------------------------------------------------------
    Total nets in design                 : 62449 (100.00%)
    Nets asserted                        : 10584 (16.95%)
    Clock nets                           : 0 (0.00%)
    Constant nets                        : 47 (0.08%)
    Nets with no assertions              : 51865 (83.05%)
    -------------------------------------------------------

     

    • Post Points: 5
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Started by dkhan at 27 Jul 2013 02:23 PM. Topic has 2 replies.