Dear all,Originally posted in cdnusers.org by vj
I'm simulating a frequency divider circuit and the criticallity of
design is the output duty-cycle. While simulating with Spectre without
any pMOS/nMOS mismatch at cross-corners I'm getting a duty-cycle of 49%
to 51%. However, at silicon the duty cycle obtained is ~43%.
Now, I want to introduce the mismatch in pMOS/nMOS devices.
Could anyone let me know how to introduce mismatch in these devices and then do the transient simulation?
All the help is appreciated.