Actually, this is documented in the Virtuoso Analog Design Environment L User Guide (in cdnshelp, or look at <ICinstDir>/doc/anasimhelp/anasimhelp.pdf ). There's a section called "How the Netlister Expands Hierarchy" which explains this. In fact Agilent's site seems to have lifted exactly the same flowchart from the ADE documentation ;-)
It also refers to the hierarchy editor user guide (from the same document), which gives more control.
The idea is that having determined how the netlister expands the hierarchy, once it reaches a stopping view, it will then use the information in the Simulation Information section of the CDF for that component to determine how the instance formatted in the netlister.
Typically the stop view is usually just a copy of the symbol, and is just a marker to tell it where to stop - it doesn't really need much information from the view itself - except the terminals. The terminals may potentially have additional (inherited) terminals for adding bulk terminals to 3 terminal transistors (for example), but in most cases the stopping view looks identical to the symbol view.