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# Problem in creating logic to electrical connect module in verilogams

Last post Tue, Jul 9 2013 2:05 PM by indra0804. 0 replies.
 Started by indra0804 09 Jul 2013 02:05 PM. Topic has 0 replies and 375 views
• #### Tue, Jul 9 2013 2:05 PM

• indra0804
• Joined on Tue, Jun 18 2013
• Posts 13
• Points 170
Problem in creating logic to electrical connect module in verilogams
 Hi, I am trying to make a logic to electrical connect module that can convert logic ( '1' or '0') at the input side to electrical pulses at the output side, implementing in verilog-ams, its required for one of the project that I am doing. But, the problem that I am having is that, its running and simulation is taking place, but irrespective of whether I give '1 or a logic '0'', the output is staying at 818.18mV. My Vhigh= 1.8 V and Vlow= 0v.I am attaching the code that I am trying to implement.... `include "disciplines.vams"`timescale 1ns / 10ps connectmodule d2a (out, in);    parameter real v0 = 0.0; // output voltage for a logic 0 (V)    parameter real v1 = 5.0; // output voltage for a logic 1 (V)    parameter real vx = 2.5; // output voltage for a logic x (V)    parameter real vz = 5.0; // output voltage for a logic z (V)    parameter real r0 = 1k from (0:inf); // output resistance for a logic 0 (Ohms)    parameter real r1 = 1k from (0:inf); // output resistance for a logic 1 (Ohms)    parameter real rx = 100 from (0:inf); // output resistance for a logic x (Ohms)    parameter real rz = 1M from (0:inf); // output resistance for a logic z (Ohms)    parameter real tr=1n from [0:inf); // rise time (s)    parameter real tf=1n from [0:inf); // fall time (s)    input in;    output out;    logic in;    electrical out;    real v, r;     assign in = in;     initial begin case(in)    1'b0: begin v = v0; r = r0; end    1'b1: begin v = v1; r = r1; end    1'bx: begin v = vx; r = rx; end    1'bz: begin v = vz; r = rz; end endcase    end     always @in begin case(in)    1'b0: begin v = v0; r = r0; end    1'b1: begin v = v1; r = r1; end    1'bx: begin v = vx; r = rx; end    1'bz: begin v = vz; r = rz; end endcase    end     analog  V(out) <+ transition(v, 0, tr, tf) + transition(r, 0, tr, tf)*I(out);endmodule  Regards, Indrajit
• Post Points: 5
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 Started by indra0804 at 09 Jul 2013 02:05 PM. Topic has 0 replies.
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