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 Problem while running verilog-ams block in cadence schematic editor 

Last post Tue, Jul 9 2013 6:18 AM by indra0804. 2 replies.
Started by indra0804 08 Jul 2013 05:31 AM. Topic has 2 replies and 798 views
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  • Mon, Jul 8 2013 5:31 AM

    • indra0804
    • Not Ranked
    • Joined on Tue, Jun 18 2013
    • Posts 13
    • Points 170
    Problem while running verilog-ams block in cadence schematic editor Reply

    Hi,

     I am little bit new to the domain of verilog-ams. I have created blocks using verilog-a and have successfully simulated them along with other components like voltage sources, resistor etc.

     Now I am trying to create a block in verilog-ams that would convert logic to electrical signal and I would like to use this block as a connect module to convert from logic to electrical.

     The code of the logic2electrical block is like this:

     

    //Verilog-AMS HDL for "Work_Indra", "logic2electrical123" "verilogams"

     

    `include "constants.vams"

    `include "disciplines.vams"

     

    `timescale 1ns / 10ps

     

    module logic2electrical123 (in,out );

     

    parameter real v0 = 0 ;

    parameter real v1 = 1.8 ;

    parameter real vx = 0.9 ;

    parameter real vz = 1.8 ;

     

    parameter real tr = 1e-09 ;

    parameter real tf = 1e-09 ;

     

        input in;

        output out;

        logic in;

        electrical out;

        real  v;

     

        assign in = in;

     

        initial begin

            case(in)

                1'b0: begin v = v0; end

                1'b1: begin v = v1; end

                1'bx: begin v = vx; end

                1'bz: begin v = vz; end

            endcase

        end

     

        always @in begin

            case(in)

                1'b0: begin v = v0; end

                1'b1: begin v = v1; end

                1'bx: begin v = vx; end

                1'bz: begin v = vz; end

            endcase

        end

     

        analog begin

            V(out) <+ transition(v, 0, tr, tf);

        end 

    endmodule

     

     The code has been compiled successfully and I am able to generate a symbol.

    Now in schematic editor I am trying to use that symbol. In the input side I have just connected a source "vbit" with logic '1' and the o/p I have connected to ground via a resistor.

     While I try to do any kind of analysis, I am getting some error like as shown in the pic attached.

     

    Regards,

     Indrajit 


    • Post Points: 20
  • Mon, Jul 8 2013 5:48 AM

    Re: Problem while running verilog-ams block in cadence schematic editor Reply

    You can't use VerilogAMS cellViews in spectre; these require "ams" as the simulator (AMS Designer) - because spectre only supports pure analog. You need a simulator with a digital engine to be able to handle the logic side.

    Regards,

    Andrew.

    • Post Points: 20
  • Tue, Jul 9 2013 6:18 AM

    • indra0804
    • Not Ranked
    • Joined on Tue, Jun 18 2013
    • Posts 13
    • Points 170
    Re: Problem while running verilog-ams block in cadence schematic editor Reply

    Hi Andrew, 

     Thank you very much. I got the point. After reading your response, I started learning about AMS Designer and tried to set up AMS environment. Had a few problems initially, but finally I was able to set up AMS design environment on ADE and run my design (consisting of both verilog and verilogams blocks) successfully.

     Couldnot use the vbit source though, had to write some code in verilog for the bit source. But would like to know more on vbit source and its use. Because, I need to get a bit pattern as input, maybe vbit can be helpful if I can get it to use.

     

    Regards,

    Indrajit 

    • Post Points: 5
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Started by indra0804 at 08 Jul 2013 05:31 AM. Topic has 2 replies.