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 Error while netlisting in UltrasimVerilog 

Last post 12-29-2006 2:47 AM by archive. 0 replies.
Started by archive 29 Dec 2006 02:47 AM. Topic has 0 replies and 1073 views
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  • 12-29-2006 2:47 AM

    • archive
    • Top 75 Contributor
    • Joined on 07-04-2008
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    Error while netlisting in UltrasimVerilog Reply

    Dear all,

    I'm doing PLL top level simulations using UltrasimVerilog simulator.
    I'm getting the following error while generating the netlist using ADE.

    ***************************************************************************************************************************
    *USRERR: PseudoTerminal [@vsub:%:not_used], of instance I0 (referring to placed master dpll_sv92ex_ver_1_0.PLLCSDMS1T12.symbol), residing in cellview (dpll_sv92ex_ver_1_0.PLLCSDMS1T12_test.schematic, using configViewString verilog schematic spectre cmos_sch cmos.sch veriloga ahdl)
    with inherited connection expression [@vsub:%:not_used]
    is connecting to default net not_used
    that is NOT A GLOBAL net.
    *Error* Failed to partition the design.
          ...unsuccessful.
    *Error*Unable to display raw netlist files.
    ****************************************************************************************************************************


    Could you please let me know the way to rectify it?


    Originally posted in cdnusers.org by vj
    • Post Points: 0
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Started by archive at 29 Dec 2006 02:47 AM. Topic has 0 replies.