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 P&R Optimization  

Last post Thu, Jul 4 2013 2:14 AM by Aram Shahinyan. 2 replies.
Started by Aram Shahinyan 03 Jul 2013 07:33 AM. Topic has 2 replies and 529 views
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  • Wed, Jul 3 2013 7:33 AM

    P&R Optimization Reply

     Dear Friends,

     I'm trying to Place and Route hand written gate verilog, but I don't want tool to optimize logic, replace gates, etc, that's why 

    I place cells with  the following option:

    placeDesign -noPrePlaceOpt

    The problem is I cannot force the tool do only signal buffering optimization. In other words I want Encounter insert only buffers

    without touching the gates I have used (e.g. do not replace MUX with AND-OR, etc)

    Please help

    Thanks,

    Aram

    • Post Points: 20
  • Wed, Jul 3 2013 10:50 AM

    • wally1
    • Top 50 Contributor
    • Joined on Mon, Aug 4 2008
    • Bellevue, WA
    • Posts 151
    • Points 2,945
    Re: P&R Optimization Reply

     Hi Aram,

    Can you try limiting optDesign to only buffer insertion by disabling upsizing/downsizing/deletion with setOptMode:

        setOptMode -downSizeInst false -upsizeInst false -deleteInst false

    Regards,

    Brian

    • Post Points: 20
  • Thu, Jul 4 2013 2:14 AM

    Re: P&R Optimization Reply

     Thanks a lot, Brian! That worked!

    Best Regards,

    Aram

    • Post Points: 5
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Started by Aram Shahinyan at 03 Jul 2013 07:33 AM. Topic has 2 replies.