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 AFA for VHDL in IFV 

Last post Mon, Jun 24 2013 3:08 AM by Buvna. 2 replies.
Started by Buvna 24 Jun 2013 01:22 AM. Topic has 2 replies and 398 views
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  • Mon, Jun 24 2013 1:22 AM

    • Buvna
    • Top 500 Contributor
    • Joined on Fri, May 31 2013
    • Posts 19
    • Points 245
    AFA for VHDL in IFV Reply

    Hey,

    I have mixed language in my design (Verilog and VHDL).

    I notice that AFA is generated only for Verilog and not VHDL. Is this a problem with the tool?

    Thanks. 

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    • Post Points: 20
  • Mon, Jun 24 2013 2:24 AM

    • JoergM
    • Top 500 Contributor
    • Joined on Thu, Jul 17 2008
    • Munich, Bavaria
    • Posts 28
    • Points 550
    Re: AFA for VHDL in IFV Reply

    Hi,

    IFV support AFA in all HDL languages including VHDL, Verilog and SystemVerilog. What you experience is either a setup or a tool problem.

    Jörg.

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    • Post Points: 20
  • Mon, Jun 24 2013 3:08 AM

    • Buvna
    • Top 500 Contributor
    • Joined on Fri, May 31 2013
    • Posts 19
    • Points 245
    Re: AFA for VHDL in IFV Reply

    Thank you for your immediate reply.

    I have used the irun command, any irun option that I could have used that could have prevented AFA for VHDL? 

    • Post Points: 5
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Started by Buvna at 24 Jun 2013 01:22 AM. Topic has 2 replies.