In my design I have an SDRAM controler which operates at 100 MHz(10ns). Along with the adddress,data and control signals, the SDRAM controller provides the clock to the external Memory chip form through IO pad. Now I have some issue with meeting the timing of my design under the following scenario.
Assume a read signal is generated by counter at positive edge of clock, now the controller expect the valid data at the next positive edge as per my design.
But the IO pad delay and Push out delay of the IO pad is around 12 ns, So I have a total delay of 12ns to both clock and address bits of the memory. But since my controller expects the data at after 10 ns ( 10ns is my clock period) I can't get valid data due to IO pad delay.
I hope I can solve the issue by skewing the clock signal at the flipflops which accepts the read data. But I don't know how to do this.
The information I'm having is summarized as below:
1) The read data will be based on a delayed clock delayed by 12 ns .
I think I can create a virtual clock, apply a latency to the same and apply the input delay at read data input ports based on the delayed virtual clock. Can anyone please help me to do this