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 Binding vhdl output ports and sv assertion module input ports in cadence simulator 

Last post Thu, Jun 6 2013 5:01 AM by rajay. 0 replies.
Started by rajay 06 Jun 2013 05:01 AM. Topic has 0 replies and 524 views
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  • Thu, Jun 6 2013 5:01 AM

    • rajay
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    Binding vhdl output ports and sv assertion module input ports in cadence simulator Reply

    Hi,

    Is there a way to bind vhdl outputs with my SV checker module  input ports? And also how do i access vhdl ports from my sv testbench?

     

    Thanks,Rajay 

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Started by rajay at 06 Jun 2013 05:01 AM. Topic has 0 replies.