Home > Community > Forums > Custom IC Design > Simulating an imported VHDL

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Simulating an imported VHDL 

Last post Thu, Aug 3 2006 3:30 AM by archive. 4 replies.
Started by archive 03 Aug 2006 03:30 AM. Topic has 4 replies and 2461 views
Page 1 of 1 (5 items)
Sort Posts:
  • Thu, Aug 3 2006 3:30 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    Simulating an imported VHDL Reply

    Hi everybody
    I'm newbie in using Cadence, so pleas forgive me if my question is too banal.
    I need to simulate, using Analog Environment, a logic component (so far it's synthetized only in VHDL) which must control an analog circuit (whose schematic is created by Virtuoso tool). To do this I've imported a VHDL file into a library of Cadence, and it created the 3 views (entity, structural, symbol). (CIW -> File -> Import -> VHDL)
    I put an instance of it in the Virtuoso schematic I want to simulate by the Analog Environment, but when I start the netlist and simulation, I receive the following error message:
    Netlister: unable to descend into any of the views defined in the view list "spectre cmos_sch cmos.sch schematic veriloga ahdl" for instance ...

    If I've uderstood, I must put in the view list in the Environment window another view, for simulating VHDL imprted, but I have no idea about which view I have to put in...
    Thanks in advance
    Paolo


    Originally posted in cdnusers.org by Delfo
    • Post Points: 0
  • Thu, Aug 3 2006 3:43 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Simulating an imported VHDL Reply

    Paolo,

    You didn't say which simulator you're trying to use, but from the view list, my guess is that it is spectre.

    If spectre, you will need a view which is netlistable - for example, a schematic or extracted type view. If it is just VHDL language, you can't simulate that in spectre.

    When doing File->Import->VHDL, you have the ability to import structural VHDL as "schematic" - did you do that? If you open the structural view that you imported, is it a schematic, or is it textual? If it is a schematic, you should be able to put "structural" in the view list. If it is textual, it's probable that the code is not really structural...

    If you were using "ams" as the simulator (AMS Designer), then you should be able to simulate it with the language code.

    Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
    • Post Points: 0
  • Fri, Aug 4 2006 2:05 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Simulating an imported VHDL Reply

    Yes, I'm using Spectre.
    I've already tried by importing the VHDL as Schematic, but it creates , together with the symbol view, an entity and a behavioral view, and both are textual. And anyway, it continues to show the same error message when I try to simulate.
    Otherwise, is there an easy way to import a logic circuit, synthetized by vhdl (just an ideal logic, at this stage I don't care about delays and power consumption), into an analog circuit and simulate all by Spectre?
    Thanks again.
    Paolo


    Originally posted in cdnusers.org by Delfo
    • Post Points: 0
  • Fri, Aug 4 2006 2:15 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Simulating an imported VHDL Reply

    Paolo,

    I'm not sure what you mean by synthesizing to "ideal logic", but unless your VHDL instantiates cells which have a transistor level description (e.g. a schematic, or included subckt) or possibly a Verilog-A model, then you cannot simulate in a circuit simulator. You'd need a mixed-signal or logic simulator to do that.

    From what you say about not caring yet about delays etc, I suspect you have not synthesized to any actual standard cells?

    Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
    • Post Points: 0
  • Fri, Aug 4 2006 2:30 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Simulating an imported VHDL Reply

    Exactly, I thought it was possible to simulate even without having to create any standard cells (the technology I'm using doesn't give the description of its standard cells).
    But if this is impossible, I'll look for other solutions.
    Thanks a lot however, Andrew.
    Best regards
    Paolo


    Originally posted in cdnusers.org by Delfo
    • Post Points: 0
Page 1 of 1 (5 items)
Sort Posts:
Started by archive at 03 Aug 2006 03:30 AM. Topic has 4 replies.