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 VERILOGA current imbalance 

Last post Wed, Jun 14 2006 1:26 AM by archive. 4 replies.
Started by archive 14 Jun 2006 01:26 AM. Topic has 4 replies and 1776 views
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  • Wed, Jun 14 2006 1:26 AM

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    VERILOGA current imbalance Reply

    I am using VERILOGA to model an operational amplifier. While testing the circuit I encountered this problem. I designed a symbol with inout port for input bias current. The current is supplied by an external idc source in analogLib and the view I used is spectre. The port is defined as electrical and inout in the veriloga program. The external current source is supplying a 100 ua current in the config schematic,while I asigned only a 10 uA in the program. Now when I simulate the config schematic by appropriate settings in the Hierachial Editor, the ciruit is simulated with no errors and gives a current of 10 uA in the transient analysis. To check the voltage imbalance case, I verified, but the simulator generates an error if voltage immbalnces exist in schematic and veriloga program. Hence what I doubt is voltage is balanced and the current is not balanced. Can anybody throw some light on this problem?? Thanks in advance for the suggestions. My veriloga program is like this. include include module diffamp(BIAS, OUTT, OUTC, INT, INC, en) inout BIAS; electrical BIAS; ......... ......... ......... analog begin ......... ........ ....... I(BIAS) <+ 10e-6; end endmodule


    Originally posted in cdnusers.org by gunturikishore28
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  • Thu, Jun 15 2006 8:58 AM

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    RE: VERILOGA current imbalance Reply

    Your question is not that clear, but I think you're asking why spectre does not complain about the fact that you have 100uA in series with 10uA?

    What is happening is that since the node is essentially floating, it has inserted a "gmin" resistor (1Tohm) from the node to ground. As a result, the two current sources are in parallel, and the resulting current will flow through the gmin resistor. You may get a warning about the fact that there's a very large voltage on the bias node - something like:

    Gmin = 1 pS is large enough to noticeably affect the DC solution.
    dV(n1) = 110 MV

    Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
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  • Thu, Jun 15 2006 6:04 PM

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    RE: VERILOGA current imbalance Reply

    Sorry for the inconvinence caused due to the poor formatting and thank you very much for the solution.

     I would like to further know, what extent the veriloga can be used to debug the problems in analog circuits by replacing the circuit with behavioral model. I tried to use it in switch capacitor circuits, but the results are quite erroneous with the current showing some unexpected values. Is it due to my poor programming skills in VERILOGA??

    Thanks in advance for you advice.


    Originally posted in cdnusers.org by gunturikishore28
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  • Fri, Jun 16 2006 1:02 AM

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    RE: VERILOGA current imbalance Reply

    Verilog-A can very successfully be used for the application you describe. It does place some responsibility on you for modelling the components properly though!

    If you've not seen it, I can recommend "The Designer's Guide to Verilog-AMS" by Ken Kundert and Olaf Zinke
    http://www.designers-guide.org/Books/#Kundert-2004 as an excellent way of getting up to speed with Verilog-A/Verilog-AMS

    Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
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  • Sun, Jun 18 2006 6:07 PM

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    RE: VERILOGA current imbalance Reply

    Thank You very much for suggestions.

    Regards,

    kishore.


    Originally posted in cdnusers.org by gunturikishore28
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Started by archive at 14 Jun 2006 01:26 AM. Topic has 4 replies.