I am using VERILOGA to model an operational amplifier. While testing the circuit I encountered this problem.
I designed a symbol with inout port for input bias current. The current is supplied by an external idc source in analogLib and the view I used is spectre. The port is defined as electrical and inout in the veriloga program. The external current source is supplying a 100 ua current in the config schematic,while I asigned only a 10 uA in the program. Now when I simulate the config schematic by appropriate settings in the Hierachial Editor, the ciruit is simulated with no errors and gives a current of 10 uA in the transient analysis.
To check the voltage imbalance case, I verified, but the simulator generates an error if voltage immbalnces exist in schematic and veriloga program. Hence what I doubt is voltage is balanced and the current is not balanced.
Can anybody throw some light on this problem??
Thanks in advance for the suggestions.
My veriloga program is like this.
module diffamp(BIAS, OUTT, OUTC, INT, INC, en)
I(BIAS) <+ 10e-6;
endmoduleOriginally posted in cdnusers.org by gunturikishore28