In a previous life, we were working with a process which was yet to be fully qualified, and for which there were no PDKs, so I wrote the pCells for layout and schematics.
Using common code between the schematic symbol and layout views allowed me to know the exact dimensions of the component given appropriate parameters (FET width and length, resistor value, capacitor value), from which parasitic effects could be determined and annotated onto the device for netlisting (via CDF parameters) eg. FET AS/AD/PS/PD, resistor parasitic cap, capacitor bottom plate cap, etc.
We had very good agreement between schematic simulation and RCX extracted simulation (and final silicon) at and above 6GHz, and our design cycles were tighter because we didn't need to go around the RCX loop as often.
With proper parameterized spectre/spice models, or a decent PDK, you don't need to do this. But if you want to work outside those models, nothing beats it.
-steveOriginally posted in cdnusers.org by stevea