I have reattached a new cts report. I cannot understand why the actual Max. Rise Sink tran and Max. Fall Sink Tran are so big (would this problem arise from incorrect library characterization?). Please see the attached file for more details.
Actual Max. Rise Sink Tran : 391862(ps)
Actual Max. Fall Sink Tran : 12150.8(ps)
Anyways, the tool will still not generate/buffer the clock tree. I also get the following message :
SubTree No: 0
Output_Net: (clock) DontTouch (Special PowerDomain Case)
Is clock tree synthesis different for MSV designs? (Either way, both my power domains are at the same voltage, I only use an additional domain to allow me to connect cells in that domain to a rail that i want to monitor, (current sensing completion detection))
In the end the clock tree is just a bunch of long wires connected to the 240 flip flops.
Any help or advice is extremely appreciated.