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 lvsIgnore of voltage source vdc 

Last post Fri, Apr 5 2013 10:53 PM by Andrew Beckett. 1 replies.
Started by navi2582 04 Apr 2013 03:52 PM. Topic has 1 replies and 634 views
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  • Thu, Apr 4 2013 3:52 PM

    • navi2582
    • Top 500 Contributor
    • Joined on Wed, May 9 2012
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    lvsIgnore of voltage source vdc Reply

    Hi,

    I have a legacy voltage source "vdc" in IC614 env, modified long time ago (set lvsIgnore to FALSE) and still works fine (gets netlisted during CDL). But, followed the same procedure (copied "vdc" from analogLib to my local directory, modified the lvsIgnore to FALSE in the symbol view) in IC615 env andit doesn't work (doesn't netlist in the CDL).

    Am I overlooking something?

    I have verified the cdfDump for the two but didn't see any difference.

    Any thoughts?

    Thanks,

    • Post Points: 20
  • Fri, Apr 5 2013 10:53 PM

    Re: lvsIgnore of voltage source vdc Reply

    You'll also need to open the auCdl view of vdc and remove the lvsIgnore and nlAction properties. Looking at my IC614 build, it was the same there too, as far as I can see.

    Certainly these properties on the stop view will be used to determine whether the component should be ignored.

    Regards,

    Andrew.

    • Post Points: 5
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Started by navi2582 at 04 Apr 2013 03:52 PM. Topic has 1 replies.