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 Verilog in and spice out procedure? 

Last post Sat, Mar 30 2013 8:31 AM by rexnyu. 0 replies.
Started by rexnyu 30 Mar 2013 08:31 AM. Topic has 0 replies and 685 views
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  • Sat, Mar 30 2013 8:31 AM

    • rexnyu
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    • Joined on Tue, Mar 26 2013
    • Posts 14
    • Points 160
    Verilog in and spice out procedure? Reply

    Dear all,

     

    I want to convert a verilog netlist into a simulatable SPICE (or HSPICE) format. I have seen people talking about verilog-In and spice out. How does this process actually work? What are the tools I should use?

     

     

    Thank you so much! 

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    • Post Points: 5
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Started by rexnyu at 30 Mar 2013 08:31 AM. Topic has 0 replies.