Home > Community > Forums > Cadence Academic Network > Multi-VDD/Power-Gated Design VerilogIn


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Multi-VDD/Power-Gated Design VerilogIn 

Last post Tue, Mar 26 2013 8:23 PM by Northfork. 0 replies.
Started by Northfork 26 Mar 2013 08:23 PM. Topic has 0 replies and 534 views
Page 1 of 1 (1 items)
Sort Posts:
  • Tue, Mar 26 2013 8:23 PM

    • Northfork
    • Not Ranked
    • Joined on Tue, Mar 26 2013
    • Ann Arbor, MI
    • Posts 6
    • Points 75
    Multi-VDD/Power-Gated Design VerilogIn Reply


    Is there a way for the multiple-vdd and/or virtual vdd nets to be properly generated during verilogIn?

    The import process relies on using the schematic and symbol definitions from the artisan_cell library that is provided to us and any cells that we have power gated or supplied a lower vdd to in the apr flow are not being properly reflected by the verilogIn process. (for example, you have an inv chain and say some of the inv are power gated (inv vdd is virtual) and the rest are not (inv vdd matches vdd supply), the schematic generated via verilogIn has all inverter's supply connected to vdd and the header is therefore unconnected). The layout/gds is correct, but lvs will be incorrect due to the schematic's difference.

    Currently we're using a brute force method and creating new schematic/symbols with the accurate port information, which works for the small test designs we have made...but is very impractical for our whole project. Wondering if there is a better way to do this.

    Any information/advice is appreciated!

    • Post Points: 5
Page 1 of 1 (1 items)
Sort Posts:
Started by Northfork at 26 Mar 2013 08:23 PM. Topic has 0 replies.