Home > Community > Forums > Logic Design > RC: set_min/max_delay breaks the constrained paths

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 RC: set_min/max_delay breaks the constrained paths 

Last post Thu, Sep 12 2013 12:15 AM by sjoshi. 3 replies.
Started by Sporadic Crash 26 Mar 2013 05:06 AM. Topic has 3 replies and 8727 views
Page 1 of 1 (4 items)
Sort Posts:
  • Tue, Mar 26 2013 5:06 AM

    • Sporadic Crash
    • Not Ranked
    • Joined on Mon, Sep 8 2008
    • Hamburg, Hamburg
    • Posts 7
    • Points 110
    RC: set_min/max_delay breaks the constrained paths Reply

    I have used following command(s) to constraint path delays on FF->FF path:

    set_max_delay -from $some_flops -to [get_pin inst/in_i*] 8

    The path that goes through [get_pin inst/in_i*] ends in a target FF. However when after the SDC command above, when I try to generate a timing report, following message is coming from RTL Compiler:

     

    rc:/> report timing -from [find / -inst *dat_reg*] -summary

     

     

                                  Pin                                        Type      Fanout Load Slew Delay Arrival   

                                                                                              (fF) (ps)  (ps)   (ps)    

    --------------------------------------------------------------------------------------------------------------------

    source_inst

      dat_reg_69/CP                                                 <<<                             0             0 R 

      dat_reg_69/Q                                                       qqq          3 19.9  227  +410     410 F 

      g15476/D                                                                                             +0     410   

      g15476/Z                                                             qqq           1  7.9  327  +250     660 R 

      g15435/D                                                                                             +0     660   

      g15435/Z                                                             qqq         1  8.9  286  +398    1058 R 

      g15419/C                                                                                             +0    1058   

      g15419/Z                                                             qqq         1  8.6  174  +193    1251 F 

      g15415/E                                                                                             +0    1251   

      g15415/Z                                                             qqq          1  8.9  410  +303    1554 R 

      g15391/C                                                                                             +0    1554   

      g15391/Z                                                             qqq         3 18.3  294  +302    1856 F 

    source_inst/dat_o[19]

    g35169/B                                                                                               +0    1856   

    g35169/Z                                                               qqq       1  8.2  276  +358    2215 F 

    g34962/C                                                                                               +0    2215   

    g34962/Z                                                               qqq          1  7.4  408  +257    2472 R 

    g34478/B                                                                                               +0    2472   

    g34478/Z                                                               qqq           4 26.8  240  +379    2851 R 

    some_inst/data_i[19] 

      g4358/E                                                                                              +0    2851   

      g4358/Z                                                              qqq          1  8.9  501  +300    3150 F 

      g4348/C                                                                                              +0    3151   

      g4348/Z                                                              qqq 3 16.6  325  +337    3487 R 

      xinst/B                                                  +0    3487   

      xinst/Z                  qqq           1 43.4  342  +390    3877 R 

      inst/in_i[9] (b)                                  +0    3877 R 

    --------------------------------------------------------------------------------------------------------------------

    Exception    : 'path_delays/zipped_path_delay_0'    8500ps

    Timing slack :    4623ps 

    Start-point  : dat_reg_69/CP

    End-point    : inst/in_i[9]

     

    (b) : Timing paths are broken.

     

     

     

    I have renamed instance and libcell names because company reasons.

    Is there a way to disable the behaviour of RTL Compiler that breaks the path, when set_min/max_delay SDC command is given?
    After the SDC command, the path from inst/in_i[9] until the FF will get unconstrained automatically, which I don't want.

    • Post Points: 20
  • Tue, Mar 26 2013 5:23 AM

    • Vinkesh
    • Not Ranked
    • Joined on Tue, Sep 9 2008
    • Noida, Uttar Pradesh
    • Posts 1
    • Points 20
    Re: RC: set_min/max_delay breaks the constrained paths Reply
    Hi,
     
    Can you try setting the below attribute? This should resolve your concern on RC breaking paths when set_max_delay is applied.--set_attribute timing_no_path_segmentation {set_max_delay} /-- Thanks

    ed!!
    • Post Points: 20
  • Tue, Mar 26 2013 7:22 AM

    • Sporadic Crash
    • Not Ranked
    • Joined on Mon, Sep 8 2008
    • Hamburg, Hamburg
    • Posts 7
    • Points 110
    Re: RC: set_min/max_delay breaks the constrained paths Reply

    I have tried following combinations:

     set_attribute timing_no_path_segmentation {set_max_delay set_data_check} /
    read_sdc <file>

    ... -> still broken paths.

    Then I tried 
    set_attr tim_ignore_data_check_for_non_endpoint_pins true /
    set_attr tim_ignore_data_check_for_non_endpoint_pins false /
    with the command above. Still broken paths.

    I have restarted RTL Compiler, before reading set the vars in any combination.
    Still broken paths.

    Tell me how to move.

    • Post Points: 20
  • Thu, Sep 12 2013 12:15 AM

    • sjoshi
    • Not Ranked
    • Joined on Wed, May 22 2013
    • Posts 1
    • Points 5
    Re: RC: set_min/max_delay breaks the constrained paths Reply

    Hi,

     Can you please check one thing.

    You may be applying max delay at a higher level of hierarchy. Just check that there might be sequential instance below that hierarchy.

    Try putting max delay from that lowest level of hierarchy ie: reg and to the lowest level of hierarchy that is reg.

    It may solve the problem.

     

    thanks,

    Shobhit 

    • Post Points: 5
Page 1 of 1 (4 items)
Sort Posts:
Started by Sporadic Crash at 26 Mar 2013 05:06 AM. Topic has 3 replies.