Home > Community > Forums > Functional Verification > IVB not supporting additional port definations for systemverilog UVC creation

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 IVB not supporting additional port definations for systemverilog UVC creation 

Last post Thu, Mar 21 2013 2:35 AM by hannes. 1 replies.
Started by pravintavagad 20 Mar 2013 04:04 AM. Topic has 1 replies and 793 views
Page 1 of 1 (2 items)
Sort Posts:
  • Wed, Mar 20 2013 4:04 AM

    • pravintavagad
    • Not Ranked
    • Joined on Tue, Jul 10 2012
    • Satara, Maharashtra
    • Posts 8
    • Points 175
    IVB not supporting additional port definations for systemverilog UVC creation Reply

    I am trying build UVC using IVB but IVB not showing Port definations dialog for Systemverilog-UVM where as it is showing it for UVM-e.

    Please help me to declare additional ports in IVB.

     

    Filed under: , , ,
    • Post Points: 20
  • Thu, Mar 21 2013 2:35 AM

    • hannes
    • Top 150 Contributor
    • Joined on Fri, Nov 14 2008
    • Bracknell, Berkshire
    • Posts 50
    • Points 895
    Re: IVB not supporting additional port definations for systemverilog UVC creation Reply
    Hi,
    you can just add your ports to the interface definition. The file is called <your_package>_if.sv in the sv directory. Once the ports are there, they can be accessed via the interface pointer in various components (e.g. vif in the driver).
    Regards,
    -hannes
    • Post Points: 5
Page 1 of 1 (2 items)
Sort Posts:
Started by pravintavagad at 20 Mar 2013 04:04 AM. Topic has 1 replies.