I have couple of doubts. Please help me out.
1. My project is about SRAM design controller. While doing compilation i can able to see(in GUI) all my modules in my design but when i synthesize it one of the sub-module(Adress Decoder-FSM module) is not available. What will be the reason for it??
2.How to define virtual clock for my combinational design module??
Thanks in advance :)