I am are doing my UG Final year project using cadence gpdk 45nm technology,
It would be of great help if someone explain and help us find a solution for the following two error messages:
=> OXIDE.A.1:Minimum area for Active area >=0.035 um
=>METAL.A.1:Metal area must be >=0.02 um
These errors pertain to vias used- nwell and psub
Could someone also brief about the vias used for nmos and pmos in gpdk 45nm technology?
Thanks in advance!