Thans for the reply. But that doesn't seem to work as it also highlights metals which are connected to transistors and normal capacitors as well as decoupling capacitors etc..
The layout was done using both layout-L and layout -XL so as such the connectivity reference of nets between the schematic and the layout might not be one to one.I think this is why it is also highlighting layout nets and devices which are connected in schematic but cadence thinks that it is unconnected in layout when I apply the above search as you suggest.
Please understand the layout is DRC clean as well as LVS checks passes successfully.
is there any other solution.
Thanks and Regards,