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 Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist 

Last post Wed, Feb 5 2014 6:37 PM by tstark. 12 replies.
Started by Rafeeq2129 06 Mar 2013 03:03 AM. Topic has 12 replies and 5780 views
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  • Wed, Mar 6 2013 3:03 AM

    • Rafeeq2129
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    Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist Reply

    I'm trying to setup flow for using CONFORMAL LEC with DC netlist, and facing few problems in mapping.

    --> Conformal doesn't map the RTL(async neg reset) with its counterpart  in netlist(DC). 

    ---> Conformal Doesn't map the "SNPS_CLOCK_GATE_HIGH" latch 

     **************my dofile is as follows (till it goes into lec mode)

         reset

        set log file <  >

         "sourcing project specific variables"

        set undefined cell black_box

          add notranslate filepathnames <  >

          add search path

          read library -verilog2k  

           read design -noelaborate -verilog2k -nosensitive  -golden <>

             read design -noelab -systemverilog -nosensitive -golden <>

          elaborate design -golden <>

          read design  -verilog 2k -revised <>

            set flatten model -nomap -latch_transparent -latch_merge_port -seq_constant -gated_clock -seq_redundant -nodff_to_dlat_zero -verbose

     set system mode lec

     

    *******************************************************************

     

    please provide me the basic flow for CONFORMAL--DC netlist

     

    regards,

    rafeeq

     

    • Post Points: 20
  • Fri, Mar 8 2013 3:22 PM

    • tstark
    • Top 200 Contributor
    • Joined on Mon, Jul 28 2008
    • San Jose, CA
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    Re: Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist Reply

    Hi, Rafeeq.

    Your best bet is to start with a standard dofile script for RTL to gate compares. Hier compare is recommended but flat can also be used.

    These sample dofiles are in the "web interface" documentation. You can access them with "set web on" and then open the browser URL in PC or linux. The WI also has a good document on verifying DC netlists. Look for "LEC Verification".

    The WI has a lot of really good documents and I find them really useful.

    Here is an example dofile

    read library -verilog -replace -both <lib_files>
    read library -liberty -replace -both <lib_files>
    read design -verilog -replace -golden <design_files>
    read design -verilog -replace -revised <design_files>
    report design data
    report black box -detail
    add pin constraint 0 scan_en -golden/revised
    add ignore output scan_out -golden/revised
    set flatten model -seq_constant
    set flatten model -gated_clock
    set analyze option -auto
    set parallel option -threads 4 -norelease_license

    // Uncomment for flat compare

    // set system mode lec

    // add compared points -all

    // compare

     

    // Hier compare after this point. 

    write hier_compare dofile hier.do -replace -usage
       -constraint -noexact_pin_match -verbose
       -prepend_string "report design data; usage;
       analyze datapath -module -resourcefile <file> -verbose; usage;
       analyze datapath -verbose; usage "
       -balanced_extraction -input_output_pin_equivalence
       -function_pin_mapping
    run hier_compare hier.do -verbose

     

    -ts

    • Post Points: 50
  • Wed, Apr 3 2013 12:17 AM

    • Rafeeq2129
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    Re: Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist Reply

     Hi Stark,

                    Thanks for providing me the basic flow. I was able to clear the aborts / unmapped points in my design using "analyze setup" , as was suggested to me in my case request.

     In the flow you mentioned, Can i use both "Flattened" and then "hierarchical flow" for my design?

    How much important is resource file for the analyze datapth command ?

     

    regards,

    rafeeq

     

    • Post Points: 20
  • Thu, Apr 4 2013 2:52 PM

    • tstark
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    Re: Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist Reply

    Glad to read.

    You can use either hier or flat for compares. Hier is better for RTL to gates since it makes for small logic cone sizes and thus helps avoid aborts. Flat is suggested for gate to gate compares (if you encounter modeling or aborts gate to gate then you can try hier).

    The resource file is useful for resolving aborts (and avoiding them in a CAD flow). For a one-off run with no aborts it is not needed.

     

    -ts

    • Post Points: 20
  • Thu, Apr 4 2013 11:33 PM

    • Rafeeq2129
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    Re: Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist Reply

     Hi ,

              thanks for information. 

            I was facing around 1900 aborts with the flat run, in which most of them seems to be the datapath optimizations. Hence, I fired the hier compare with the flow you suggested, along with resource file . the end result was 2 aborts.

                  I want to check all the equiv./non-eq/aborts of the whole design, and diagnise it. But, I'm unable to find the doc. which gives specific information on debug of hier-result. Although there is a chapter in user-guide, it mostly guides about running flow using GUI. Could you please help me on it ?

     

    regards.

    rafeeq

     

    • Post Points: 20
  • Fri, Apr 5 2013 12:15 PM

    • tstark
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    Re: Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist Reply

    There is a lot of good debug material in the "Web Interface".

    Type "SETUP> set web on" and view in a browser. See Abort Resolution and LEC Verification.

     

    Also see the LEC debugging quickstart video:

    http://trainingondemand.cadence.com

     

    -ts

    • Post Points: 20
  • Mon, Apr 8 2013 12:00 AM

    • Rafeeq2129
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    Re: Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist Reply

     Hi ,

             i'm unable to opne the http link which the command "set web on" is generating. The hyper link i snothing but my machine on which tool is running. Is it the expected link ?

     

    regards,

    rafeeq

     

    • Post Points: 20
  • Mon, Apr 8 2013 10:25 AM

    • tstark
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    Re: Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist Reply

    The server is launched from within the tool. The serve will close when the tool closes so keep the tool open.

    If you still have problems then file a support ticket (http://support.cadence.com)

     

    -ts

    • Post Points: 5
  • Mon, Apr 15 2013 12:14 AM

    • Rafeeq2129
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    Re: Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist Reply

    Hi,

          In the above mentioned flow, I can see the "flatten model"commands  uncommented. Does it mean that the modeling commands are also used for hierarchical comparison ? 

     

    regards,

    rafeeq

     

    • Post Points: 20
  • Thu, Apr 18 2013 5:00 PM

    • tstark
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    Re: Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist Reply

     Yes. By default the flatten model commands will be used by both hier and flat compares. (Whenever changing from setup mode to lec mode. This is done in the generated hier script.)

    -ts

    • Post Points: 5
  • Wed, Feb 5 2014 4:56 AM

    • Rafeeq2129
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    Re: Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist Reply

    Hi,

     

    I'm facing error while applying 'prepend string' command in tcl mode, along with write hier_compare command.

    How do i apply the above command in tcl mode.

     

    Regards,

    Rafeeq

     

    • Post Points: 35
  • Wed, Feb 5 2014 11:47 AM

    • grasshopper
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    Re: Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist Reply

     Hi Rafeeq,

     the main problem you may have is that TCL does not have a 'prepend' command but it is hard to guess without you providing any output of what message you are getting. For a list of TCL commands, please refer to

    http://www.tcl.tk/man/tcl8.5/

    hope this helps,

    gh-

    • Post Points: 5
  • Wed, Feb 5 2014 6:37 PM

    • tstark
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    Re: Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist Reply

     You should be able to use this option with write_hier_compare_dofile in TCL. It will have to be valid TC, escaped etc.

     Maybe try with something simple first and verify it works.

    There are some small sample testcases in the installation tree:

    share/cfm/lec/demo

    If it is too much of a problem try going into VPX mode (not TCL mode):

    vpxmode

    write hier_compare dofile ...

    run hier

    tclmode

     

    -ts

    • Post Points: 5
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Started by Rafeeq2129 at 06 Mar 2013 03:03 AM. Topic has 12 replies.