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 Layout problem with nMOS transistors N_BPW_12_LLNVT 65 nm UMC 

Last post Wed, Feb 27 2013 6:23 AM by Quek. 1 replies.
Started by ingenier7 25 Feb 2013 12:16 PM. Topic has 1 replies and 536 views
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  • Mon, Feb 25 2013 12:16 PM

    • ingenier7
    • Not Ranked
    • Joined on Mon, Feb 25 2013
    • Posts 1
    • Points 20
    Layout problem with nMOS transistors N_BPW_12_LLNVT 65 nm UMC Reply

    Hi everybody,

    I am having a problem with transistors nMOS model N_BPW_12_LLNVT in 65 nm UMC.

    These transistors are triple-well. This is the first time I am using them and although my layout passes the DRC rules and
    the LVS, when I simulate it in post-layout level, the DC voltages of my circuit goes to values different than the ones obtained
    in schematic level. I suppose I am connecting wrong any of the wells of the transistor.

    Has anyone used this kind of transistors or any triple well technology? I would like to know how I have to bias it.
    I want to used the bulk as an input.

    Thanks in advance.

    • Post Points: 20
  • Wed, Feb 27 2013 6:23 AM

    • Quek
    • Top 10 Contributor
    • Joined on Wed, Oct 14 2009
    • Singapore, 00-SG
    • Posts 1,069
    • Points 16,275
    Re: Layout problem with nMOS transistors N_BPW_12_LLNVT 65 nm UMC Reply

    Hi ingenier7

    I think it might be better for you to contact UMC foundry support for this question. : )  They should be able to provide a good answer.

    Best regards
    Quek

    • Post Points: 5
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Started by ingenier7 at 25 Feb 2013 12:16 PM. Topic has 1 replies.