Home > Community > Forums > Mixed-Signal Design > error during IE generation(mixed signal simulation)

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 error during IE generation(mixed signal simulation) 

Last post Sun, Mar 24 2013 4:59 AM by Andrew Beckett. 4 replies.
Started by RAMYA1 25 Feb 2013 02:08 AM. Topic has 4 replies and 751 views
Page 1 of 1 (5 items)
Sort Posts:
  • Mon, Feb 25 2013 2:08 AM

    • RAMYA1
    • Not Ranked
    • Joined on Mon, Feb 25 2013
    • Posts 4
    • Points 65
    error during IE generation(mixed signal simulation) Reply
    I have created a project in virtuoso in which i had schematics and verilog codes. All these analog schematics and digital blocks are instantiated in anoyher schematic in the same project. I choose mixed signal simulation option (verimix) . Under verimix, i have given partion options, IE library and selected IE cells.(analogLib->MOS),

    In ADE, in setup design- i have given the config of topcell. simulator-spectreverilog.

    I am getting following error during netlist generation---- error in interface element generation.

    Can you suggest me any corrections.

    Can you also suggest me how to change the design so that i will avoid the mixed signals.

    Please find the log file screenshot in the attachment.

    I have also tried to instantiate MOS_d2a and MOS_a2d in my design. Input of MOS_a2d is pure analog but output is a mixed signal. Reason i thought is---- In verimix, under partitioning options i gave spectre under analog partition. so, as the MOS_a2d has the view spectre, it is considered as analog block so the output is a mixed signal instead of digital.

    I also tried not giving spectre in analog partition, but iam getting error.

    Please can you suggest me any solution for instantiating MOS_a2d without making it a part of either analog or digital partition.

    Also please help me to solve the error in IE(Interface Element) generarion.

    Thanks & Regards,
    RAMYA

    • Post Points: 20
  • Mon, Feb 25 2013 9:49 AM

    Re: error during IE generation(mixed signal simulation) Reply

    Is there a reason why you're using the really old "verimix" (spectreVerilog) simulator as opposed to "ams" (AMS Designer) which is much newer and supports far more in terms of language support? spectreVerilog is essentially obsolete...

    I'm not sure of the reason for the failure (without doing research that I don't have time to do right now unfortunately) - if you really can't use AMS Designer, I'd suggest you contact customer support.

    Kind Regards,

    Andrew.

    • Post Points: 20
  • Wed, Feb 27 2013 8:39 PM

    • RAMYA1
    • Not Ranked
    • Joined on Mon, Feb 25 2013
    • Posts 4
    • Points 65
    Re: error during IE generation(mixed signal simulation) Reply

    hai,

              I have changed my simulator to ams. Now iam having  verilogams codes and schematic in my design.Netlist generation is working well. But elaboration is skipped. Can you suggest any idea when this happens. Can you also give me an example stimulus file for simulation to undertand the syntax.

     Thanks&Regards,

    RAMYA

    • Post Points: 5
  • Wed, Feb 27 2013 9:44 PM

    • RAMYA1
    • Not Ranked
    • Joined on Mon, Feb 25 2013
    • Posts 4
    • Points 65
    Re: error during IE generation(mixed signal simulation) Reply

    hai,

        Iam able to get the elabotaion. But during simulation iam getting x/z in digital domain which cannot be converted in analog domain.

    I think this is because i didn't provide any stimulus file. So, please provide me an example stimuls file to know the syntax. If it is due to timing, please suggest me a solution.

     

    Thanks&Regards,

    RAMYA

    • Post Points: 20
  • Sun, Mar 24 2013 4:59 AM

    Re: error during IE generation(mixed signal simulation) Reply

    Not sure what "stimulus file" you're talking about. It may be a spectre syntax file, or you may want to have some Verilog code, or you may just put sources from analogLib in to drive your circuit. Your mileage may vary.

    Andrew.

    • Post Points: 5
Page 1 of 1 (5 items)
Sort Posts:
Started by RAMYA1 at 25 Feb 2013 02:08 AM. Topic has 4 replies.