I have created a project in virtuoso in which i had schematics and verilog codes. All these analog schematics and digital blocks are instantiated in anoyher schematic in the same project. I choose mixed signal simulation option (verimix) . Under verimix, i have given partion options, IE library and selected IE cells.(analogLib->MOS),
In ADE, in setup design- i have given the config of topcell. simulator-spectreverilog.
I am getting following error during netlist generation---- error in interface element generation.
Can you suggest me any corrections.
Can you also suggest me how to change the design so that i will avoid the mixed signals.
Please find the log file screenshot in the attachment.
I have also tried to instantiate MOS_d2a and MOS_a2d in my design. Input of MOS_a2d is pure analog but output is a mixed signal. Reason i thought is---- In verimix, under partitioning options i gave spectre under analog partition. so, as the MOS_a2d has the view spectre, it is considered as analog block so the output is a mixed signal instead of digital.
I also tried not giving spectre in analog partition, but iam getting error.
Please can you suggest me any solution for instantiating MOS_a2d without making it a part of either analog or digital partition.
Also please help me to solve the error in IE(Interface Element) generarion.
Thanks & Regards,