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 Customized Schematic Generation Using Skill 

Last post Thu, Feb 21 2013 5:55 AM by Quek. 1 replies.
Started by T Opperman 21 Feb 2013 02:16 AM. Topic has 1 replies and 418 views
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  • Thu, Feb 21 2013 2:16 AM

    • T Opperman
    • Not Ranked
    • Joined on Fri, Feb 15 2013
    • Posts 7
    • Points 125
    Customized Schematic Generation Using Skill Reply

    I need to think of ways to generate top level circuit schematics using skill. I thought about using verilogIn, but I later realized that it does not provide me with much flexibility, and it does not allow me to map specific libraries to specific module/cell instances. What also happens is that I have symbols form different libraries with different pin lists that has the same module/cell names.

    So as I looked through the sch* functions in skill, I was unable to identify a straightforward method to instance a symbol in a schematic, and specify labeled wires to be connected its pins. It doesn't have to be routed. I suppose one can go about opening each symbol to obtain its pin locations/labels, but it seems a bit tedious and prone to bugs. Does anyone know of any higher level functions to do this?

    Regards,

    Tjaart

    • Post Points: 20
  • Thu, Feb 21 2013 5:55 AM

    • Quek
    • Top 10 Contributor
    • Joined on Wed, Oct 14 2009
    • Singapore, 00-SG
    • Posts 1,060
    • Points 16,110
    Re: Customized Schematic Generation Using Skill Reply

    Hi Tjaart

    How about simply querying each symbol to get the terminal/pin info?

    symbolID~>master~>terminals~>name

    Hope that I am not misunderstanding your question. Or are you looking for schSymbolToPinList function?

    schSymbolToPinList("myLib" "myCell" "symbol")

    Best regards
    Quek

    • Post Points: 5
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Started by T Opperman at 21 Feb 2013 02:16 AM. Topic has 1 replies.