I am integrating SystemC module with SystemVerilog verification environment. One of the SystemC module has an array of sc_in and sc_out ports, for which I am creating a Verilog wrapper with corresponding input and output ports.
Though the code compiles properly with command line "irun -sv <sv_files> -sysc <sysc_files>", I am getting an elaboration error at the place where an array of Verilog wires are used to bind to the SystemC array of ports though its SV wrapper. Binding is at signal level only.
Please suggest if there is any way to connect the SystemC array of signal level ports to a Verilog/SystemVerilog module.
Thanks and Regards,