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 CTS and timing analysis for generated clock 

Last post Fri, Feb 1 2013 10:06 AM by gops. 0 replies.
Started by gops 01 Feb 2013 10:06 AM. Topic has 0 replies and 732 views
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  • Fri, Feb 1 2013 10:06 AM

    • gops
    • Top 75 Contributor
    • Joined on Wed, Sep 24 2008
    • Trivandrum, Kerala
    • Posts 118
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    CTS and timing analysis for generated clock Reply

    I have a clock scenario as shown below.

     I have defined the B, A as clocks and X as generated clock. In my design X is 300KHz and A is 200 MHz and B is 50 MHz. Sel 2 will switch on the fly during the chip opreation. ie the FFs driven by CLK needs to be run at 300KHz initially and soon after a period it will switch to either 200MHz or 50 MHz. The sel1 is an input pad so it will be a predetermined value.

     

    I want to know how will the ETS engine computes the hold time and set up time. I'm getting a clock gating check error as hold violation at the FF driven by the CLK pin. WIll ETS check the setup and hold analysis for 300 KHz , 50 MHz and 200 MHz clocks for the FFs driven by CLK. 

     

    Should I need to do anything particular to handle this issue in the most apropriate way while building the clock tree and  ETS while analyzing the timing. Thanks in advance

    gops


    • Post Points: 5
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Started by gops at 01 Feb 2013 10:06 AM. Topic has 0 replies.