I am not sure I understand the question. Ultimately, what do you expect the tools to do if your HDL says
always @(posedge clk1) begin
dataout <= clk2
. . .
similarly for the reset case. The lint report (report timing -lint -verbobse) will warn you about this but it ultimately up to the user to specify the design correctly. The HDL is correct and there is no other way to implement than to use clk2 as specified in HDL so other than warning you I am not sure what else can the tools do
hope this helps,