Hope I can explain this well enough. Does anyone know of a "tool" that EE's or SI eng's can use to add constraints to a design. I'm thinking of a tool that could parse net names from a schematic or netlist and the EE could group them or attach them to an existing CM ECset or whatever. Something easier to use than the Allegro CM and could be run outside of the Allegro environment. I saw a tool used that would extract net names by sorting or wildcard and the SI Eng could grab them and apply constraints to them. Either previously used/created constraints or create a new constraint. The tool would then create a bunch of files that would be read in with the netlist. Some engineers do the CM input themselves, some give you a piece of paper, some want it on the schematic, and some are "same as" it worked before type. I've worked with SI engineers that did not want their constraints dink-ed with at all by anyone.
So does anyone know of a tool either 3rd party or Cadence that works this way that is not to complicated?