In the .libs, generated clock statements help defining the internal clocks being used in the entire design. When the .lib is design, internal clocks are reported or defined with the hierarchy of its instance, with a lot of complex naming conventions.
Is there a way to control the naming conventions..
a generated clock g1, is internal clock of IP lib ( IP_A). IP_A is for example is instanced under U_A_m/U_B_sm/U_C_sm
g1 clock definition in the design is reported as U_A_m\/U_B_sm\/U_C_sm\/U_IP_A\/g1
The above definition makes the further constraints defining very difficult in the flow on these clocks.
Is there a way to instruct the RC tool to honor then naming of the clock defined by the user as oppose the tool giving its own names .
Thanks for the help!!