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 Does test compaction reduces tester time or memory or both? 

Last post Thu, Jan 10 2013 5:20 AM by vipul982. 2 replies.
Started by vipul982 02 Jan 2013 10:41 PM. Topic has 2 replies and 684 views
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  • Wed, Jan 2 2013 10:41 PM

    • vipul982
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    Does test compaction reduces tester time or memory or both? Reply
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  • Thu, Jan 3 2013 9:01 AM

    • bmiller
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    Re: Does test compaction reduces tester time or memory or both? Reply

     Please clarify if you are referring to hardware compression (hardware inserted into the chip to split long fullscan chains into shorter scan channels), or software compaction (ATPG technique to reduce pattern count).

     I guess the answer isn't that important, because both techniques will reduce both tester time and memory, although software compaction is not nearly effective as hardware compression logic.   Software compaction nearly "free", however, as it only consumes runtime.   The only other downside to software compaction is a possible increase in the power consumption of a pattern.

     

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  • Thu, Jan 10 2013 5:20 AM

    • vipul982
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    Re: Does test compaction reduces tester time or memory or both? Reply
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Started by vipul982 at 02 Jan 2013 10:41 PM. Topic has 2 replies.