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 CONFORMAL LEC- MODULES SKIPPED FROM HIER. BCOZ OFEXTRA PORTS AFTER MBIST INSERTION  

Last post Thu, Nov 29 2012 9:07 AM by SWAROOP24X7. 0 replies.
Started by SWAROOP24X7 29 Nov 2012 09:07 AM. Topic has 0 replies and 870 views
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  • Thu, Nov 29 2012 9:07 AM

    CONFORMAL LEC- MODULES SKIPPED FROM HIER. BCOZ OFEXTRA PORTS AFTER MBIST INSERTION Reply
    Hi all,

    I'm doing logical equivalence check between
    1)RTL n MBIST inserted NETLIST
    2)PLAIN NETLIST without MBIST n DFT stuffs vs MBIST inserted NETLIST
    TEST_MODE is a top level pin of my design which when 0 makes the design in pure functional mode.My design is very complex and I'm moving with hierarchial comparison.So dpends on tool generated script.My issue is in the revised netlist there are many registers extra..which are the output ports of internal modules.So when i did

    add pin constraints 0 TEST_MODE -revised
    write hier dofile LEC.do -constraint -noexact -replace

    since golden has no mbist cells many internal modules are skipped from hierarchial script(dofile).And when compared at the higher hierarchy of design it gave me many non equivalent points.So that the TEST_MODE 0 value cant be propagated.Please if anyone knows the solution please do reply

    Please help,i'm in the critical stage of the project.
    • Post Points: 5
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Started by SWAROOP24X7 at 29 Nov 2012 09:07 AM. Topic has 0 replies.